ADUC7023BCPZ62I Datasheet, PDF (76/96 Pages) Analog Devices – Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler

ADuC7023
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 22 interrupt sources on the ADuC7023 that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals, such as ADC. Four
additional interrupt sources are generated from external interrupt
request pins, IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI
CPU core only recognizes interrupts as one of two types, a
normal interrupt request IRQ or a fast interrupt request FIQ.
All the interrupts can be masked separately.
The control and configuration of the interrupt system is managed
through nine interrupt related registers, four dedicated to IRQ,
and four dedicated to FIQ. An additional MMR is used to select
the programmed interrupt source. The bits in each IRQ and
FIQ registers represent the same interrupt source as described
in Table 88.
The ADuC7023 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting is enabled by setting the ENIRQN bit
in the IRQCONN register. A number of extra MMRs are used
when the full-vectored interrupt controller is enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 88. IRQ/FIQ MMRs Bit Description
Bit
Description
0
All interrupts OR’ed (FIQ only).
1
SWI.
2
Timer0.
3
Timer1.
4
Watchdog timer (Timer 2).
5
Flash control.
6
ADC channel.
7
PLL lock.
8
I²C0 master.
9
I²C0 slave.
10
I²C1 master.
11
I²C1 slave.
12
SPI.
13
External IRQ0.
14
Comparator.
15
PSM.
16
External IRQ1.
17
PLA IRQ0.
18
External IRQ2.
19
External IRQ3.
20
PLA IRQ1.
21
PWM.
Data Sheet
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are: IRQSTA, IRQSIG,
IRQEN, and IRQCLR.
IRQSTA Register
Name:
IRQSTA
Address:
0xFFFF0000
Default value: 0x00000000
Access:
Read
Function:
IRQSTA (read-only register) provides the
current-enabled IRQ source status. When
set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no
priority encoder or interrupt vector
generation. This function is implemented in
software in a common interrupt handler
routine. All 32 bits are logically OR’ed to
create the IRQ signal to the ARM7TDMI
core.
IRQSIG Register
Name:
IRQSIG
Address:
0xFFFF0004
Default value: 0x00XXX000
Access:
Read
Function:
IRQSIG reflects the status of the different IRQ
sources. If a peripheral generates an IRQ
signal, the corresponding bit in the IRQSIG is
set; otherwise, it is cleared. The IRQSIG bits
are cleared when the interrupt in the
particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR.
IRQSIG is read-only.
Rev. E | Page 76 of 96