TVP3025 Datasheet, PDF (74/99 Pages) Texas Instruments – Video Interface Palette

Table 2–28. Status Register (RS value = 11010)
BIT
NAME
VALUES
DESCRIPTION
SR07 Reserved (logic 0)
0: Idle
SR06
1: Busy
BT485 register translation state machine indicator. If this bit is a logic 1, then
the TVP3020 index registers should not be accessed.
SR05,
SR04
Revision bit values
These two bits are for revision numbers. Initially they contain zeros.
SR03 SENSE bit
SENSE bit. If it is a logic 0, one or more of the IOR, IOG, and IOB outputs have
exceeded the internal voltage reference. See Section 2.4.14.
SR02
SR01,
SR00
0: Write cycle
1: Read cycle
00: Red color component
01: Green color component
10: Blue color component
Read/write cycle status. This bit provides read/write status when the register
select bits 0, 3, 4, or 7 (hex) have been written.
These bits reflect the color component address of the next read/write cycle
when the palette, cursor color, or overscan registers are accessed.
2.4.16.3 Accessing Command Registers 3 and 4
A fourth and fifth command register, command register 3 and command register 4 are added to address the
extended functions of the TVP3025 and remain backward compatible with the BT485. Since there are only
4 register select lines defined on the BT485 (all 16 combinations are used), command register 3 and
command register 4 must be accessed indirectly. Command registers 3 and 4 are accessed with the
following sequence of operations:
1. Set RS3 – RS0 to 0110, command register 0.
2. Write a logic 1 to CR07.
3. Set RS3 – RS0 to 0000, address register.
4. Write address register to 0000 0001 (command register 3) or 0000 0010 (command register 4).
5. Set RS3 – RS0 to 1010.
6. Read or write command register 3 or 4.
With this indirect addressing, the status register can be accessed by writing 0000 0000 to the address
register, as in step 4 above.
To address the 64 × 64 cursor RAM, CR31 and CR30 must be written to provide the 2 MSBs for the 10-bit
address counter. Therefore, to set the counter to access a particular location in the RAM array, these 2 bits
must be written to command register 3 before the lower 8 bits are written to the address counter through
the MPU port. As the 10-bit address counter auto-increments, the new value of this counter can be read back
through CR31 and CR30. The contents of this register are reset with the assertion of the external RESET
terminal. See Section 2.4.15.5 and the notes in that section.
2.4.16.4 Cursor-Position (x,y) Registers
These registers are used to specify the (x,y) coordinates of the 64 × 64 × 2 hardware cursor. The cursor
registers contain low and high value registers. The last value written by the MPU to these registers is the
value returned on a read. These registers can be read/written by the MPU at any time. Bits D4 – D7 of both
high registers are ignored.
Data Bit
X Position
CURSOR-POSITION X HIGH
CURSOR-POSITION X LOW
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0
RS value = 11101
RS value = 11100
2–60