XIO2213A_10 Datasheet, PDF (73/186 Pages) Texas Instruments – PCI Express to 1394b OHCI with 3-Port PHY

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XIO2213A PCI Express to 1394b OHCI with 3-Port PHY
SCPS183A – OCTOBER 2007 – REVISED MARCH 2008
4.58 Serial-Bus Slave Address Register
The serial-bus slave address register indicates the slave address of the device being targeted by the
serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register
initiates the cycle on the serial interface. See Table 4-32 for a complete description of the register
contents.
PCI register offset:
B2h
Register type:
Read/Write
Default value:
00h
BIT NUMBER
RESET STATE
76543210
00000000
Table 4-32. Serial-Bus Slave Address Register Descriptions
BIT
FIELD NAME
7:1⁽¹⁾ SLAVE_ADDR
0⁽¹⁾ RW_CMD
ACCESS
RW
RW
DESCRIPTION
Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write
transaction. The default value for this field is 000 0000b.
Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.
0 = A single byte write is requested (default).
1 = A single byte read is requested.
(1) This register shall only be reset by a Fundamental Reset (FRST).
4.59 Serial-Bus Control and Status Register
The serial-bus control and status register controls the behavior of the serial-bus interface. This register
also provides status information about the state of the serial bus. See Table 4-33 for a complete
description of the register contents.
PCI register offset:
Register type:
Default value:
BIT NUMBER
7
RESET STATE
0
B3h
Read-only, Read/Write, Read/Clear
00h
6543210
0000000
Table 4-33. Serial-Bus Control and Status Register Description
BIT
FIELD NAME
7⁽¹⁾ PROT_SEL
6
RSVD
5⁽¹⁾ REQBUSY
4⁽¹⁾ ROMBUSY
ACCESS
RW
R
RU
RU
DESCRIPTION
Protocol select. This bit selects the serial-bus address mode used.
0 = Slave address and word address are sent on the serial-bus (default)
1 = Only the slave address is sent on the serial-bus
Reserved. Returns 0b when read.
Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle
is in progress.
0 = No serial-bus cycle
1 = Serial-bus cycle in progress
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge
is downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
(1) This register shall only be reset by a Fundamental Reset (FRST).
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Classic PCI Configuration Space
73