TSB43AB21A Datasheet, PDF (72/116 Pages) Texas Instruments – Integrated 1394a-2000 OHCI PHY/Link-Layer Controller

4.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the TSB43AB21A device
is cycle master, this register is transmitted with the cycle start message. When the TSB43AB21A device is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message
is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
See Table 4–26 for a complete description of the register contents.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Isochronous cycle timer
Type
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
Default X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous cycle timer
Type
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
Default X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BIT
31–25
24–12
11–0
Register:
Offset:
Type:
Default:
Isochronous cycle timer
F0h
Read/Write/Update
XXXX XXXXh
Table 4–26. Isochronous Cycle Timer Register Description
FIELD NAME
cycleSeconds
cycleCount
cycleOffset
TYPE
RWU
RWU
RWU
DESCRIPTION
This field counts seconds [rollovers from bits 24–12 (cycleCount field)] modulo 128.
This field counts cycles [rollovers from bits 11–0 (cycleOffset field)] modulo 8000.
This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz clock
configuration is being used, this field must be cleared to 0s at each tick of the external clock.
4–30