TMS320VC5410A Datasheet, PDF (70/100 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G – NOVEMBER 2000 – REVISED JANUARY 2005
www.ti.com
5.9 Ready Timing for Externally Generated Wait States
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13).
Table 5-13. Ready Timing Requirements for Externally Generated Wait States⁽¹⁾
5410A-120
5410A-160
MIN MAX
UNIT
t_su(RDY)
t_h(RDY)
t_v(RDY)MSTRB
t_h(RDY)MSTRB
t_v(RDY)IOSTRB
t_h(RDY)IOSTRB
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low⁽²⁾
Hold time, READY after MSTRB low⁽²⁾
Valid time, READY after IOSTRB low⁽²⁾
Hold time, READY after IOSTRB low⁽²⁾
7
ns
0
ns
4H – 4 ns
4H
ns
4H – 4 ns
4H
ns
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
(2) These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States⁽¹⁾
PARAMETER
5410A-120
5410A-160
MIN MAX
UNIT
t_d(MSCL)
t_d(MSCH)
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
–1
4 ns
–1
4 ns
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
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Electrical Specifications