CC1110FX_08 Datasheet, PDF (70/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller

CC1110Fx / CC1111Fx
Interrupt Number
0
16
8
1
9
2
10
3
11
4
12
5
13
6
7
14
15
17
Interrupt Name
RFTXRX
RF
DMA
ADC
T1
URX0
T2
URX1 / I2SRX
T3
ENC
T4
ST
P0INT / (USB Resume)
P2INT / USB
UTX0
URX1 / I2STX
P1INT
WDT
Polling sequence
Table 43: Interrupt Polling Sequence
11 Debug Interface
The CC1110Fx/CC1111Fx includes an on-chip
debug module which communicates over a
two-wire interface. The debug interface allows
programming of the on-chip flash. It also
provides access to memory and registers
contents, and debug features such as
breakpoints, single-stepping, and register
modification.
The debug interface uses the I/O pins P2_1 as
Debug Data and P2_2 as Debug Clock during
Debug mode. These I/O pins can be used as
general purpose I/O only while the device is
not in Debug mode. Thus the debug interface
does not interfere with any peripheral I/O pins.
11.1 Debug Mode
Debug mode is entered by forcing two rising
edge transitions on pin P2_2 (Debug Clock)
while the RESET_N input is held low.
While in Debug mode pin P2_1 is the Debug
Data bi-directional pin and P2_2 is the Debug
Clock input pin.
Note: Debugging of PM2 and PM3 is not
supported. Also note that CLKCON.CLKSPD
must be 000 or 001 when using the debug
interface
11.2 Debug Communication
The debug interface uses an SPI-like two-wire
interface consisting of the P2_1 (Debug Data)
and P2_2 (Debug Clock) pins. Data is driven
on the bi-directional Debug Data pin at the
positive edge of Debug Clock and data is
sampled on the negative edge of this clock.
Debug commands are sent by an external host
and consist of 1 to 4 output bytes (including
command byte) from the host and an optional
input byte read by the host. Command and
data is transferred with MSB first. Figure 17
shows a timing diagram of data on the debug
interface.
SWRS033G
Page 70 of 244