UCC28528 Datasheet, PDF (7/32 Pages) Texas Instruments – ADVANCED PFC/PWW COMBINATION CONTROLLER WITH TRAILING-EDGE/TRAILING-EDGE MODULATION

UCC28521, UCC28528
SLUS608B − JANUARY 2005 REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
T_A = –40°C to 105°C for the UCC2851x, T_A = T_J, VCC = 12 V, R_T = 156 kΩ, R_{CT_BUFF} = 10 kΩ
(unless otherwise noted)
PWM stage overcurrent limit
PARAMETER
Peak current comparator threshold voltage
Input bias current(1)
TEST CONDITIONS
MIN
1.15
TYP
1.30
50
MAX
1.45
UNITS
V
nA
PWM stage gate driver
PARAMETER
TEST CONDITIONS
GT2 pull-up resistance
GT2 pull-down resistance
GT2 output rise time
GT2 output fall time
−100 mA ≤ ∆IOUT ≤ −200 mA
IOUT = 100 mA
CLOAD = 1 nF,
RLOAD = 10 Ω
1. Ensured by design. Not 100% tested in production.
MIN
TYP
MAX UNITS
5
12 Ω
2
10 Ω
16
25 ns
7
15 ns
NAME
CAOUT
TERMINAL
NO.
15
Stage
PFC
CT_BUFF
5
PWM
D_MAX
GND
GT1
GT2
IAC
ISENSE1
ISENSE2
MOUT
PKLMT
PWRGND
RT
SS2
VAOUT
VCC
VERR
4
PWM
6
−
12
PFC
10
PWM
18
PFC
16
PFC
8
PWM
17
PFC
14
PFC
11
−
2
−
13
PWM
1
PFC
9
−
7
PWM
VFF
VREF
VSENSE
19
PFC
20
−
3
PFC
TERMINAL FUNCTIONS
I/O
DESCRIPTION
O
Output of the current control amplifier of the PFC stage. CAOUT is internally connected
to the PWM comparator input in the PFC stage
O
Internally buffered PWM stage oscillator ramp output, typically used to program slope
compensation with a single resistor
I
Positive input to set the maximum duty cycle clamp level of the PWM stage duty ratio
can be between 0.09 and 0.90.
−
Analog ground
O
PFC stage gate drive output
O
PWM stage gate drive output
I
Multiplier current input that is proportional to the instantaneous rectified line voltage
I
Non-inverting input to the PFC stage current amplifier
I
Input for PWM stage current sense and peak current limit
I/O
PFC multiplier high−impedance current output, internally connected to the current am-
plifier inverting input
I
Voltage input to the PFC peak current limit comparator
−
Power ground for GT1, GT2 and high current return paths
I
Oscillator programming pin that is set with a single resistor to GND
I
Soft start for the PWM stage
I/O
Output of the PFC transconductance voltage amplifier and it is internally connected to
the Zero Power Detect comparator input and the multiplier input
I
Positive supply voltage pin
I
Feedback error voltage input for the PWM stage, typically connected to an optocoupler
output
I
Voltage feedforward pin for the PFC stage, sources an IAC/2 current that should be
externally filtered
O
Precision 7.5-V reference output
I
Inverting input to the PFC transconductance voltage amplifier, and input to the OVP,
ENABLE and UVLO2 comparators
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