TPS40132 Datasheet, PDF (7/40 Pages) Texas Instruments – TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER WITH INTEGRATED MOSFET DRIVERS

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RHB PACKAGE
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TPS40132
SLUS776A – DECEMBER 2007 – REVISED FEBRUARY 2008
BOOT1
OVSET
VOUT
GSNS
DIFFO
CS1
CSRT1
COMP
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
89
10
11
12 13
14
15
17
16
BOOT2
SS
UVLO
BP5
AGND
CS2
CSRT2
RT
TERMINAL
NAME
NO.
AGND
20
BOOT1
1
BOOT2
24
BP5
21
BP8
13
COMP
8
CS1
6
CS2
19
CSRT1
7
CSRT2
18
DIFFO
5
+EA
10
EN/SYNC
14
FB
11
GSNS
4
HDRV1
32
Terminal Functions
I/O
DESCRIPTION
- Low noise ground connection to the device.
Provides a bootstrapped supply for the high-side FET driver for PWM1, enabling the gate of the high-side
I FET to be driven above the input supply rail. Connect a capacitor from this pin to SW1 pin and a Schottky
diode from this pin to VIN5.
Provides a bootstrapped supply for the high-side FET driver for PWM2, enabling the gate of the high-side
I FET to be driven above the input supply rail. Connect a capacitor from this pin to SW2 pin and a Schottky
diode from this pin to VIN5.
I
Filtered input from the VIN5 pin. A 10-Ω resistor should be connected between VIN5 and BP5 and a 1.0-µF
ceramic capacitor should be connected from this pin to ground.
Output of the LDO that powers the differential amplifier and the current sense amplifiers. The voltage is
O approximately (V_VDD -0.2 V) until the output regulates at approximately 7.5 V. Decouple this pin with a
minimum capacitance of 1.0-µF to GND.
O Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM.
I These pins are used to sense the inductor phase current. Inductor current can be sensed with an external
current sense resistor or by using an external R-C circuit and the inductor's DC resistance. The traces for
I ^{these signals must be connected directly at the current sense element. See Layout Guidelines for more}
information.
I _{Return point of current sense voltage. The traces for these signals must be connected directly at the}
I ^{current sense element. See Layout Guidelines for more information.}
Output of the differential amplifier. The voltage at this pin represents the true output voltage without IR
O drops that result from high-current in the PCB traces. The VOUT and GSNS pins must be connected
directly at the point of load where regulation is required. See Layout Guidelines for more information.
I
This is the input to the non-inverting input of the Error Amplifier. This pin is normally connected to the
VREF pin and is the voltage that the feedback loop regulates to.
I
A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes
the rising edge of SW to the falling edge of an external clock source.
I
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal
reference level of 600 mV. This pin is also used for the PGOOD and undervoltage comparators.
I Inverting input of the differential amplifier. This pin should be connected to ground at the point of load.
O
Gate drive output for the high-side N-channel MOSFET switch for PWM1. Output is referenced to SW1 and
is bootstrapped for enhancement of the high-side switch.
Copyright © 2007–2008, Texas Instruments Incorporated
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