TMS320F28032 Datasheet, PDF (7/127 Pages) Texas Instruments – Piccolo Microcontrollers

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2.2 Signal Descriptions
TMS320F28032, TMS320F28033
TMS320F28034, TMS320F28035
Piccolo Microcontrollers
SPRS584A – APRIL 2009 – REVISED MAY 2009
Table 2-2. TERMINAL FUNCTIONS⁽¹⁾
TERMINAL
NAME
PN
PIN #
PAG
PIN #
TRST
10
8
TCK
TMS
TDI
TDO
TEST2
See GPIO38
See GPIO36
See GPIO35
See GPIO37
38
30
XCLKOUT
See GPIO18
XCLKIN
See GPIO19 and
GPIO38
X1
52
41
X2
51
40
I/O/Z
DESCRIPTION
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or driven
low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
I
normal device operation. An external pulldown resistor is recommended on this pin.
The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since
this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application. (↓)
I
See GPIO38. JTAG test clock with internal pullup (↑)
I
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
input is clocked into the TAP controller on the rising edge of TCK. (↑)
I
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
selected register (instruction or data) on a rising edge of TCK. (↑)
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
O/Z register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA
drive)
FLASH
I/O Test Pin. Reserved for TI. Must be left unconnected.
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This
O/Z
is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to
3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1
pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN
I
path must be disabled by bit 13 in the CLKCTL register.
Note: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for
normal device operation may need to incorporate some hooks to disable this path
during debug using the JTAG connector. This is to prevent contention with the TCK
signal, which is active during JTAG debug sessions. The zero-pin internal oscillators
may be used during this time to clock the device.
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
I
resonator must be connected across X1 and X2. In this case, the XCLKIN path must
be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to
GND. (I)
O
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
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