THS4531A_15 Datasheet, PDF (7/59 Pages) Texas Instruments – THS4531A Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier

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THS4531A
SLOS823B – DECEMBER 2012 – REVISED JUNE 2015
Electrical Characteristics: V_S = 2.7 V (continued)
Test conditions at T_A ≈ 25°C, V_S+ = 2.7 V, V_S– = 0 V, V_OCM = open, V_OUT = 2 V_PP, R_F = 2 kΩ, R_L = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and output referenced to mid-supply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEST
LEVEL
Input bias current⁽²⁾
Input bias current drift⁽¹⁾
Input offset current
Input offset current drift⁽¹⁾
INPUT
T_A = 25°C
T_A = 0°C to +70°C
T_A = –40°C to +85°C
T_A = –40°C to +125°C
T_A = 0°C to +70°C
T_A = –40°C to +85°C
T_A = –40°C to +125°C
T_A = 25°C
T_A = 0°C to +70°C
T_A = –40°C to +85°C
T_A = –40°C to +125°C
T_A = 0°C to +70°C
T_A = –40°C to +85°C
T_A = –40°C to +125°C
200
250
A
275
nA
286
B
305
0.45 0.55
0.45 0.55 nA/°C
B
0.45 0.55
–50
±5
50
A
–55
55
nA
–57
57
B
–60
60
–0.1
±0.03
0.1
–0.1
±0.03
0.1 nA/°C
B
–0.1
±0.03
0.1
Common-mode input low
Common-mode input high
Common-mode rejection ratio
T_A = 25°C, CMRR > 87 dB
T_A = –40°C to +125°C, CMRR > 87 dB
T_A = 25°C, CMRR > 87 dB
T_A = –40°C to +125°C, CMRR > 87 dB
V_S– – 0.2
V_S–
V
A
V_S– – 0.2
V_S–
B
V_S+ – 1.2 V_S+ – 1.1
V_S+ – 1.2 V_S+ – 1.1
A
V
B
90
116
dB
A
Input impedance differential mode
200 || 1
kΩ || pF
C
OUTPUT
Single-ended output voltage: low
T_A = 25°C
T_A = –40°C to +125°C
V_S– +
0.06
V_S– +
0.2
A
V
V_S– +
0.06
V_S– +
0.2
B
Single-ended output voltage: high
T_A = 25°C
T_A = –40°C to +125°C
V_S+ – 0.2
V_S+ – 0.2
V_S+ –
0.11
V_S+ –
0.11
A
V
B
Output saturation voltage: high/low
110/60
mV
C
Linear output current drive
POWER SUPPLY
T_A = 25°C, R_L = 6 Ω
T_A = –40°C to +125°C
±15
±22
±15
A
mA
B
Specified operating voltage
2.5
2.7
5.5 V
B
Quiescent operating current/ch
Power-supply rejection (PSRR)
T_A = 25°C, PD = V_S+
T_A = –40°C to +125°C, PD = V_S+
230
330
A
µA
270
370
B
87
108
dB
A
POWER DOWN
Enable voltage threshold
Specified on above 2.1 V
2.1 V
A
Disable voltage threshold
Specified off below 0.7 V
0.7
V
A
Disable pin bias current
Power-down quiescent current
Turnon time delay
PD = V_S– + 0.5 V
PD = V_S– + 0.5 V
Time from PD = high to V_OUT = 90% of final
value, R_L= 200 Ω
50
500 nA
A
0.5
2 µA
A
650
ns
C
(2) Positive current is out of the device inputs.
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