THMC50 Datasheet, PDF (7/32 Pages) Texas Instruments – REMOTE/LOCAL TEMPERATURE MONITOR AND FAN CONTROLLER WITH SMBus INTERFACE

THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
ac electrical characteristics, V_CC3 = V_(VCC3AUX) = 3.3 V, T_A = 25°C (see Notes 6 and 7) (unless
otherwise noted)
temperature-to-digital converter timing parameters: Remote_Diode+, Remote_Diode–
PARAMETER
TEST CONDITIONS MIN TYP MAX UNITS
t(SAMPLE)
Temperature-to-digital acquisition sample rate
0.75
1 1.25 sa/s
reset function timing parameters: VCC3, VCC3AUX, MR, AUXRST, RST
PARAMETER
TEST CONDITIONS
t(RP)
t(VCC3RST)
t(VCC3AUX1)
t(VCC3AUX2)
t(MR)
t(RST)
t(MRMIN)
t(AUXRSTMIN)
t(GLITCH)
RST and AUXRST pulse duration
VCC3 to RST delay
VCC3AUX to AUXRST delay
VCC3AUX to RST delay
MR input to RST delay
AUXRST input to RST delay
MR input minimum pulse width
AUXRST input minimum pulse width
MR, AUXRST glitch immunity
See Figures 17–20
See Figures 17–20
See Figures 17–20
See Figures 17–20
See Figures 17–20
See Figures 17–20
MIN TYP MAX UNITS
140
560 ms
20
µs
20
µs
20
µs
0.5
µs
0.5
µs
10
µs
10
µs
100
ns
SMBus interface timing parameters: SCL, SDA
PARAMETER
TEST CONDITIONS MIN TYP MAX UNITS
f(SCL)
SCL operating frequency
See Figure 1
10
t(BUF)
Bus free time between stop and start condition
See Figure 1
4.7
t(HDSTA)
Hold time after (repeated) start condition. After this period,
the first clock is generated
See Figure 1
4
100 kHz
µs
µs
t(SUSTA)
Repeated start condition setup time
See Figure 1
4.7
µs
t(SUSTO)
Stop condition setup time
See Figure 1
4
µs
t(HDDAT)
Data hold time
See Figure 1
300
ns
t(SUDAT)
Data setup time
See Figure 1
250
ns
t(LOW)
SCL clock low period
See Figure 1
4.7
µs
t(HIGH)
SCL clock high period
See Figure 1
4
50 µs
t(LOWSEXT)
Cumulative clock low extend time (slave device)
See Figure 1
25 ms
t(LOWMEXT)
Cumulative clock low extend time (master device)
See Figure 1
10 ms
tF
Clock/data fall time
See Figure 1
300 ns
tR
Clock/data rise time
See Figure 1
1000 ns
NOTES: 6. Typicals are at TJ = TA = 25°C with V(VCC3AUX) = 3.3 V and represent most likely parametric norm.
7. Timing specifications are tested at the TTL logic levels, VIL = 0.4 V for a falling edge and VIH = 2.4 V for a rising edge. The 3-state
output voltage is forced to 1.4 V.
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