SN74LVCZ161284A_05 Datasheet, PDF (7/11 Pages) Texas Instruments – 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

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SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES358B – SEPTEMBER 2001 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
From
B or Y Output
Under Test
V_CC CABLE
62 Ω
C_L = 50 pF
(see Note A)
TP1
Sink Load
Source Load
62 Ω
C_L = 50 pF
(see Note A)
Input
(see Note B)
2.7 V
0V
t_f1
Output
(see Note B)
95% (V_CC CABLE = 5 V"0.5 V)
50% (V_CC CABLE = 5 V"0.5 V)
t_r1
Output
(see Note B)
1.9 V (V_CC CABLE = 5 V"0.5 V)
0.4 V
VOLTAGE WAVEFORMS MEASURED AT TP1
SLEW RATE WAVEFORMS (B8−B1 AND Y13−Y9)
SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE)
V_CC CABLE
TP1
From
B or Y Output
500 Ω
C_L = 50 pF
(see Note A)
Input
(see Note C)
1.4 V
1.4 V
2.7 V
0V
Output
(see Note C)
2V
0.8 V
t_r
2V
0.8 V
t_f
V_OH
V_OL
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN)
NOTES: A. C_L includes probe and jig capacitance.
B. When V_CC CABLE is 3.3 V " 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and
1.9 V for the falling edge. When V_CC CABLE is 5 V " 0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge and
between 95% V_CC CABLE and 50% V_CC CABLE for the falling edge.
ǒ Ǔ t_slew fall + V_CC
95% *
t_f1
50%
ǒ Ǔ t_slew rise +
1.9 V – 0.4 V
t_r1
C. Input rise (t_r) and fall (t_f) times are 3 ns. Rise and fall times (open drain) are <120 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd.
Figure 2. Load Circuits and Voltage Waveforms
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