SN74LVC16373A_06 Datasheet, PDF (7/15 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVC16373A
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L
(see Note A)
V_LOAD
R_L
S1
Open
GND
R_L
TEST
t_PLH/t_PHL
t_PLZ/t_PZL
t_PHZ/t_PZH
S1
Open
V_LOAD
GND
LOAD CIRCUIT
V_CC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
INPUTS
V_I
t_r/t_f
V_CC
V_CC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V_M
V_CC/2
V_CC/2
1.5 V
1.5 V
V_LOAD
2 × V_CC
2 × V_CC
6V
6V
C_L
30 pF
30 pF
50 pF
50 pF
R_L
1 kΩ
500 Ω
500 Ω
500 Ω
V_∆
0.15 V
0.15 V
0.3 V
0.3 V
Input
t_w
V_I
V_M
V_M
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Timing Input
Data Input
V_I
V_M
0V
t_su
V_M
t_h
V_I
V_M
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
V_M
V_I
V_M
0V
t_PLH
Output
V_M
t_PHL
V_OH
V_M
V_OL
t_PHL
t_PLH
Output
V_OH
V_M
V_M
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
V_M
V_M
t_PZL
Output
t_PLZ
Waveform 1
S1 at V_LOAD
(see Note B)
V_M
V_OL + V_∆
Output
Waveform 2
S1 at GND
(see Note B)
t_PZH
t_PHZ
V_M
V_OH − V_∆
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V_I
0V
V_LOAD/2
V_OL
V_OH
≈0 V
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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