ISO7520_1 Datasheet, PDF (7/15 Pages) Texas Instruments – Low-Power 5 KV(rms) Dual Digital Isolators

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ISO7520
ISO7521
SLLSE39 – JUNE 2010
ELECTRICAL CHARACTERISTICS
V_CC1 and V_CC2 at 3.3 V ± 5%, T_A = –40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN TYP
V_OH
High-level output voltage
I_OH = –4 mA; See Figure 1
I_OH = –20 µA; See Figure 1
V_CC –0.4
3
V_CC –0.1
3.3
V_OL
Low-level output voltage
I_OL = 4 mA; See Figure 1
I_OL = 20 µA; See Figure 1
0.2
0
V_I(HYS) Input threshold voltage hysteresis
400
I_IH
High-level input current
I_IL
Low-level input current
INx at 0 V or V_CC
–10
CMTI Common-mode transient immunity V_I = V_CC or 0 V; See Figure 3
25
40
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7520
I_CC1
Supply current for V_CC1
DC to 1 Mbps V_I = V_CC or 0 V, 15 pF load
0.2
I_CC2
Supply current for V_CC2
DC to 1 Mbps V_I = V_CC or 0 V, 15 pF load
2
ISO7521
I_CC1
Supply current for V_CC1
DC to 1 Mbps V_I = V_CC or 0 V, 15 pF load
1.5
I_CC2
Supply current for V_CC2
DC to 1 Mbps V_I = V_CC or 0 V, 15 pF load
1.5
MAX UNIT
V
0.4
V
0.1
mV
µA
µA
kV/µs
0.7 mA
4.5 mA
3.5 mA
3.5 mA
SWITCHING CHARACTERISTICS
V_CC1 and V_CC2 at 3.3 V ± 5%, T_A = –40°C to 105°C
PARAMETER
t_PLH, t_PHL
PWD ⁽¹⁾
t_sk(pp)
t_sk(o)
t_r
t_f
t_fs
Propagation delay time
Pulse width distortion |t_PHL – t_PLH|
Part-to-part skew time
Channel-to-channel output skew time
Output signal rise time
Output signal fall time
Fail-safe output delay time from input power loss
(1) Also known as pulse skew.
TEST CONDITIONS
See Figure 1
See Figure 1
See Figure 2
MIN TYP MAX UNIT
12
20 ns
1
5 ns
6 ns
5.5 ns
2
ns
2
ns
6
ns
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ISO7520 ISO7521
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