DAC5689_15 Datasheet, PDF (7/50 Pages) Texas Instruments – 16-BIT, 800 MSPS 2x–8x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5689
www.ti.com
SLLS989A – SEPTEMBER 2009 – REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS (Digital Specifications)
Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, DVDD, CLKVDD = 1.8V, Iout_FS = 20 mA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB, DA[15:0], DB[15:0], SYNC, TXENABLE, CLKO_CLK1
CONFIG26 io_1p8_3p3 = 0 (3.3V levels)
2.30
V_IH
High-level input voltage
CONFIG26 io_1p8_3p3 = 1 (1.8V levels)
1.25
V
V_IL
Low-level input voltage
CONFIG26 io_1p8_3p3 = 0 (3.3V levels)
CONFIG26 io_1p8_3p3 = 1 (1.8V levels)
1.00
V
0.54
I_IH
High-level input current
I_IL
Low-level input current
C_I
CMOS Input capacitance
SDO, SDIO, CLKO
V_OH
SDO, SDIO, CLKO
I_LOAD = –100 mA
I_LOAD = –2 mA
±20
mA
±20
mA
2
pF
IOVDD –
0.2
V
0.8 ×
IOVDD
SDO, SDIO, CLKO
V_OL
SDO, SDIO, CLKO
Input data rate
I_LOAD = 100 mA
I_LOAD = 2 mA
0.2
V
0.5
0
250 MSPS
t_s(SDENB) Setup time, SDENB to rising edge of SCLK
20
ns
t_s(SDIO)
Setup time, SDIO valid to rising edge of SCLK
10
ns
t_h(SDIO)
Hold time, SDIO valid to rising edge of SCLK
5
ns
t_SCLK
Period of SCLK
100
ns
t_SCLKH
High time of SCLK
40
ns
t_SCLK
Low time of SCLK
40
ns
t_d(Data)
Data output delay after falling edge of SCLK
10
ns
t_RESET
Minimum RESETB pulse width
25
ns
TIMING PARALLEL DATA INPUT TO CLK1/C (DUAL CLOCK and DUAL SYNCHRONOUS CLOCK MODES: Figure 28)
t_s
Setup time
t_h
Hold time
CLK1/C = input
1
ns
1
ns
t_align
Max timing offset between CLK1 and CLK2
rising edges
DUAL SYNCHRONOUS BUS MODE only
(Typical characteristic)
1
- 0.55
2f
ns
CLK 2
TIMING PARALLEL DATA INPUT TO CLKO (EXTERNAL CLOCK MODE: Figure 29)
t_s
Setup time
t_h
Hold time
t_d(CLKO)
Delay time
CLOCK INPUT (CLK2/CLK2C)
CLKO_CLK1 = output. Note: Delay time
increases with higher capacitive loads.
CLK2/C Duty cycle
CLK2/C Differential voltage⁽¹⁾
CLK2/C Input common mode
CLK2C Input Frequency
CLOCK INPUT (CLK1/CLK1C)
CLK1/C Duty cycle
CLK1/C Differential voltage
CLK1/C Input common mode
CLK1/C Input Frequency
CLOCK OUTPUT (CLKO)
CLKO Output frequency⁽²⁾
with 10pF load
1
1
4.5
40%
0.4
1
2/3 × CLKVDD
40%
0.4
1.0
IOVDD / 2
ns
ns
ns
60%
800
V
V
MHz
60%
250
V
V
MHz
185 MHz
(1) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.
(2) Specified by design and simulation. Not production tested. It is recommended to buffer CLKO.
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5689
Submit Documentation Feedback
7