CY54FCT573T_08 Datasheet, PDF (7/12 Pages) Texas Instruments – 8-BIT LATCHES WITH 3-STATE OUTPUTS

From Output
Under Test
CL = 50 pF
(see Note A)
CY54FCT573T, CY74FCT573T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS068 – OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
Test
Point
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω ^S1
500 Ω
7V
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
Input
tw
1.5 V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Timing Input
1.5 V
0V
th
tsu
3V
Data Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
3V
1.5 V
0V
Output
Control
3V
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
1.5 V
tPHL
VOH
1.5 V
VOL
tPHL
tPLH
Out-of-Phase
Output
1.5 V
1.5 V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPZL
Output
Waveform 1
(see Note B)
tPZH
1.5 V
tPLZ
≈3.5 V
VOL + 0.3 V _VOL
tPHZ
Output
Waveform 2
(see Note B)
1.5 V
VOH – 0.3 V ^VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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