CD54HC73_07 Datasheet, PDF(7/15 Page) Texas Instruments – Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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CD54HC73_07 Datasheet, PDF (7/15 Pages) Texas Instruments – Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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CD54HC73, CD74HC73, CD74HCT73

Test Circuits and Waveforms (Continued)

trCL

CLOCK

INPUT

DATA

INPUT

tSU(H)

90%

10%

tH(H)

tfCL

50%

tH(L)

tSU(L)

VCC

GND

VCC

50%

GND

OUTPUT

tREM

VCC

SET, RESET

OR PRESET

tTLH

90%

tPLH

50%

tTHL

90%

50%

10%

tPHL

GND

50pF

trCL

CLOCK

INPUT

2.7V

0.3V

tfCL

1.3V

tH(H)

tH(L)

DATA

INPUT

tSU(H)

1.3V

tSU(L)

OUTPUT

tREM

SET, RESET

OR PRESET

tTLH

90%

1.3V

tPLH

1.3V

tTHL

90%

1.3V

10%

tPHL

50pF

GND

FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

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