CD54HC597_07 Datasheet, PDF(7/18 Page) Texas Instruments – High-Speed CMOS Logic 8-Bit Shift Register with Input Storage

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CD54HC597_07 Datasheet, PDF (7/18 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Shift Register with Input Storage

◁

CD54HC597, CD74HC597, CD74HCT597

Switching Speciï¬cations Input tr, tf = 6ns (Continued)

PARAMETER

TEST

25oC

-40oC to 85oC -55oC to 125oC

SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

MR to Q7

tPLH, tPHL CL = 50pF

4.5

CL = 15pF

Output Transition Time

tTLH, tTHL CL = 50pF

4.5

Input Capacitance

CL = 50pF

Power Dissipation

CPD

Capacitance, (Notes 3, 4)

- 18.5 -

NOTES:

3. CPD is used to determine the dynamic power consumption, per package.

4. PD = CPD VCC2 fi + Î£ (CL VCC2 fo) where: fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply

Voltage.

Test Circuits and Waveforms

trCL

CLOCK

90%

10%

tfCL

50%

10%

tWL

tWH

fCL

50%

tWH

VCC

GND

trCL = 6ns

CLOCK

2.7V

0.3V

tfCL = 6ns

tWL

tWH

fCL

1.3V

0.3V

1.3V

GND

tWL

tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns

INPUT

90%

50%

10%

tf = 6ns

VCC

GND

tTHL

INVERTING

OUTPUT

tPHL

tTLH

90%

50%

10%

tPLH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tr = 6ns

INPUT

tTHL

2.7V

1.3V

0.3V

INVERTING

OUTPUT

tPHL

tf = 6ns

GND

tTLH

90%

1.3V

10%

tPLH

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

▷