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CD54HC4094_10 Datasheet, PDF (7/19 Pages) Texas Instruments – HIgh-Speed CMOS Logic 8-Stage Shift and Store Bus Register,Three-State
◁
CD54HC4094, CD74HC4094, CD74HCT4094
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
Output Enable to Qn
tPZH, tPZL CL = 50pF
2
-
- 175
-
220
-
265
ns
4.5
-
-
35
-
44
-
53
ns
6
-
-
30
-
37
-
45
ns
Output Disable to Qn
tPHZ, tPLZ CL = 50pF
2
-
- 125
-
155
-
190
ns
4.5
-
-
25
-
31
-
38
ns
6
-
-
21
-
26
-
32
ns
Output Transition Time
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Output Disabling Time
tPHZ, tPLZ CL =15pF
Maximum CP Frequency
fMAX CL =15pF
Input Capacitance
CIN CL = 50pF
Power Dissipation Capacitance CPD CL =15pF
(Notes 4, 5)
5
-
10
-
-
-
-
-
ns
5
-
60
-
-
-
-
-
MHz
-
-
-
10
-
10
-
10
pF
5
-
90
-
-
-
-
-
pF
Three-State Output
Capacitance
CO CL = 50pF
-
-
-
15
-
15
-
15
pF
HCT TYPES
Propagation Delay Time
(Figure 1)
tPLH,
tPHL
CL = 50pF
CP to QS1
CL =15pF
CP to QS2
tPLH,
tPHL
CL = 50pF
CL =15pF
CP to Qn
tPLH,
tPHL
CL = 50pF
CL =15pF
STR to Qn
tPLH,
tPHL
CL = 50pF
Output Enable to Qn
tPZH, tPZL CL = 50pF
Output Disable to Qn
tPHZ, tPLZ CL = 50pF
Output Transition Time
tTLH, tTHL CL = 50pF
Output Disabling Time
tPHZ, tPLZ CL =15pF
Maximum CP Frequency
fMAX CL =15pF
Input Capacitance
CIN CL = 50pF
Power Dissipation Capacitance CPD CL =15pF
(Notes 4, 5)
4.5
-
-
39
-
-
-
-
ns
5
-
16
-
-
-
-
-
ns
4.5
-
-
36
-
-
-
-
ns
5
-
15
-
-
-
-
-
ns
4.5
-
-
43
-
-
-
-
ns
5
-
18
-
-
-
-
-
ns
4.5
-
-
39
-
-
-
-
ns
4.5
-
-
35
-
-
-
-
ns
4.5
-
-
35
-
-
-
-
ns
4.5
-
-
15
-
-
-
-
ns
5
-
14
-
-
-
-
-
ns
5
-
60
-
-
-
-
-
MHz
-
-
-
10
-
10
-
10
pF
5
- 110 -
-
-
-
-
pF
Three-State Output
Capacitance
CO CL = 50pF
-
-
-
15
-
15
-
15
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per register.
5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
7
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