CD54HC40103_07 Datasheet, PDF (7/16 Pages) Texas Instruments – High-Speed CMOS Logic 8-Stage Synchronous Down Counters

CD54HC40103, CD74HC40103, CD74HCT40103
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
SYMBOL CONDITIONS (V)
25^oC
-40^oC TO
85^oC
MIN TYP MAX MIN MAX
-55^oC TO
125^oC
MIN MAX UNITS
MR to TC
t_PLH,
C_L = 50pF
4.5
-
-
55
-
69
-
83
ns
t_PHL
C_L = 15pF
5
-
23
-
-
-
-
-
ns
Output Transition Time
t_THL, t_TLH C_L = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C_IN
C_L = 50pF
-
-
-
10
-
10
-
10
pF
CP Maximum Frequency
f_MAX
C_L = 15pF
5
-
25
-
-
-
-
-
MHz
Power Dissipation Capacitance
C_PD
-
(Notes 4, 5)
5
-
27
-
-
-
-
-
pF
NOTES:
3. Noncascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enables (PE or TE)-to-clock SET
UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC de-
vices:
C_P
f_MAX
=
-----------------------------------------------------------------------------------------¹-------------------------------------------------------------------------------------------
CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time
=
6^----0^{-----+-----13---}0^-----+-----0^-
≈
11 M H z
4. C_PD is used to determine the dynamic power consumption, per package.
5. P_D = V_CC2 f_i + C_L V_CC2 f_o where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage, f_o = Output Frequency.
Timing Diagrams
CP
MR
TE
PE
PL
P0
P1
P2
P3
P4
P5
P6
P7
TC
HC/HCT40103 COUNT 255 254 3 2 1 0 255 254 254 253 8 7 6 5 4 255 254 253 252
FIGURE 1.
7