CD54HC192_08 Datasheet, PDF (7/18 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

CD54/74HC192, CD54/74HC193, CD54/74HCT193
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
CPD to Q_n
PL to Q_n
MR to Q_n
Transition Time
Q, TCU, TCD
t_PLH, t_PHL C_L = 50pF
2
-
- 220
-
270
-
325
ns
C_L = 50pF
4.5 -
-
43
-
54
-
65
ns
C_L = 15pF
5
- 18 -
-
-
-
ns
C_L = 50pF
6
-
- 37
-
46
-
55
ns
t_PLH, t_PHL C_L = 50pF
2
-
- 220
-
275
-
330
ns
C_L = 50pF
4.5 -
-
44
-
55
-
66
ns
C_L = 15pF
5
- 18 -
-
-
-
-
ns
C_L = 50pF
6
-
- 37
-
47
-
56
ns
t_PHL C_L = 50pF
2
-
- 200
-
250
-
300
ns
C_L = 50pF
4.5 -
-
40
-
50
-
60
ns
C_L = 15pF
5
- 17 -
-
-
-
-
ns
C_L = 50pF
6
-
- 34
-
43
-
51
ns
t_TLH, t_THL C_L = 50pF
2
-
- 75
-
95
-
110
ns
4.5 -
-
15
-
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_IN
C_L = 50pF
-
-
-
10
-
10
-
10
pF
C_PD
C_L = 15pF
5
- 40 -
-
-
-
-
pF
HCT TYPES
Propagation Delay
CPU to TCU
CPU to TCD
CPU to Q_n
CPD to Q_n
PL to Q_n
MR to Q_n
Transition Time
Q, TCU, TCD
t_PLH, t_PHL C_L = 50pF
4.5 -
-
27
-
34
-
41
ns
C_L = 15pF
5
- 11 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
4.5 -
-
27
-
34
-
41
ns
C_L = 15pF
5
- 11 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
4.5 -
-
40
-
50
-
60
ns
C_L = 15pF
5
- 17 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
4.5 -
-
40
-
50
-
60
ns
C_L = 15pF
5
- 17 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
4.5 -
-
46
-
58
-
69
ns
C_L = 15pF
5
- 21 -
-
-
-
-
ns
t_PHL C_L = 50pF
4.5 -
-
43
-
54
-
65
ns
C_L = 15pF
5
- 18 -
-
-
-
-
ns
t_TLH, t_THL C_L = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_IN
C_L = 50pF
-
-
-
10
-
10
-
10
pF
C_PD
C_L = 15pF
5
- 50 -
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per gate.
4. P_D = V_CC2 f_i + ∑ (C_L V_CC2) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
7