CD54HC112_08 Datasheet, PDF(7/18 Page) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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CD54HC112_08 Datasheet, PDF (7/18 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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CD54HC112, CD74HC112, CD54HCT112, CD74HCT112

Test Circuits and Waveforms (Continued)

tr = 6ns

INPUT

tTHL

90%

50%

10%

INVERTING

OUTPUT

tPHL

tf = 6ns

VCC

GND

tTLH

90%

50%

10%

tPLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

trCL

CLOCK

INPUT

DATA

INPUT

tSU(H)

90%

10%

tH(H)

tfCL

50%

tH(L)

tSU(L)

VCC

GND

VCC

50%

GND

OUTPUT

tREM

VCC

SET, RESET

OR PRESET

tTLH

90%

tPLH

50%

tTHL

90%

50%

10%

tPHL

GND

tr = 6ns

INPUT

tTHL

2.7V

1.3V

0.3V

INVERTING

OUTPUT

tPHL

tf = 6ns

GND

tTLH

90%

1.3V

10%

tPLH

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

trCL

CLOCK

INPUT

2.7V

0.3V

tfCL

1.3V

tH(H)

tH(L)

DATA

INPUT

tSU(H)

1.3V

tSU(L)

GND

OUTPUT

tREM

SET, RESET

OR PRESET

tTLH

90%

1.3V

tPLH

1.3V

tTHL

90%

1.3V

10%

tPHL

GND

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

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