ADS5474 Datasheet, PDF (7/38 Pages) Texas Instruments – 14-Bit, 400-MSPS Analog-to-Digital Converter

ADS5474
www.ti.com
TIMING INFORMATION
Sample
N–1
t_a
N
CLK
t_CLKH
SLAS525 – JULY 2007
N+2
N+1
t_CLKL
N+3
N+4
N+5
CLK
DRY
Latency = 3.5 Clock Cycles
t_DRY
DRY⁽¹⁾
D[13:0], OVR
D[13:0], OVR
N–1
t_DATA
N
N+1
(1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS⁽¹⁾
Typical values at T_A = +25°C: minimum and maximum values over full temperature range T_MIN = –40°C to T_MAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-V_PP differential
clock, unless otherwise noted.
t_a
t_CLK
t_CLKH
t_CLKL
t_DRY
t_DATA
t_SKEW
t_RISE
t_FALL
PARAMETER
Aperture delay
Aperture jitter, rms
Latency
Clock period
Clock pulse duration, high
Clock pulse duration, low
CLK to DRY delay⁽²⁾
CLK to DATA/OVR delay⁽²⁾
DATA to DRY skew
DRY/DATA/OVR rise time
DRY/DATA/OVR fall time
TEST CONDITIONS
Internal jitter of the ADC
Zero crossing, 10-pF parasitic loading to GND on each
output pin
Zero crossing, 10-pF parasitic loading to GND on each
output pin
t_DATA – t_DRY, 10-pF parasitic loading to GND on each output
pin
10-pF parasitic loading to GND on each output pin
10-pF parasitic loading to GND on each output pin
MIN
2.5
1
1
1000
TYP
200
103
3.5
1400
MAX
50
1800
800 1400 2000
–500
0 500
500
500
UNIT
ps
fs
cycles
ns
ns
ns
ps
ps
ps
ps
ps
(1) Timing parameters are assured by design or characterization, but not production tested.
(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to t_DATA to determine the overall propagation
delay.
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