TAS5508PAGRG4 Datasheet, PDF (69/105 Pages) Texas Instruments – 8-Channel Digital Audio PWM Processor

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6 Serial-Control I²C Register Summary
TAS5508
8-Channel Digital Audio PWM Processor
SLES091D – FEBRUARY 2004 – REVISED JULY 2009
The TAS5508 slave address is 0x36. See Serial-Control Interface Register Definitions, Section 7 for
complete bit definitions.
Note that u indicates unused bits.
I²C
SUBADDRESS
0x00
0x01
0x02
0x03
0x04
0x05–0x0C
0x0D
0x0E
0x0F
0x10–0x13
0x14
0x15
0x16
0x17–0x1A
0x1B–0x22
0x23
0x24–0x3F
0x40
TOTAL
BYTES
1
1
1
1
1
1/reg.
1
1
1
1
1
1
1/reg.
1
4
REGISTER FIELDS
Clock control register
General status register
Error status register
System control register 1
System control register 2
Channel configuration
control registers
Headphone configuration
control register
Serial data interface control
register
Soft mute register
Automute control register
Automute PWM threshold
and back-end reset period
register
Modulation index limit
register
Interchannel delay registers
Channel offset register
Bank-switching command
register
DESCRIPTION OF CONTENTS
DEFAULT STATE
Set data rate and MCLK frequency
Clip indicator and ID code for the
TAS5508
PLL, SCLK, LRCLK, and frame slip
errors
PWM high pass, clock set, unmute
select, PSVC select
Automute and de-emphasis control
Configure channels 1, 2, 3, 4, 5, 6, 7,
and 8
Configure headphone output
Set serial data interface to
right-justified, I²S, or left-justified.
Soft mute for channels 1, 2, 3, 4, 5, 6,
7, and 8
Reserved
Set automute delay and threshold.
Set PWM automute threshold; set
back-end reset period.
Set modulation index.
1. Fs = 48 kHz
2. MCLK = 256 Fs = 12.288 MHz
0x01
No errors
1. PWM high pass disabled
2. Auto clock set
3. Hard unmute on clock error recovery
4. PSVC Hi-Z disabled
1. Automute time-out disabled
2. Post-DAP detection automute enabled
3. 8-Ch device input detection automute enabled
4. Unmute threshold 6 dB over input
5. No de-emphasis
1. Enable back-end reset.
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Do not remap the output for the TAS5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
1. Disable back-end reset sequence.
2. Valid does not have to be low for reset.
3. Valid does not have to be low for mute.
4. Normal BEPolarity
5. Do not remap output to comply with 5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
24-bit I²S
Unmute all channels.
1. Set automute delay = 5 ms.
2. Set automute threshold less than bit 8.
1. Set the PWM threshold the same as the TAS5508
input threshold.
2. Set back-end reset period = 5 ms.
97.7%
Reserved
Set interchannel delay.
Absolute delay offset for channel 1
(0–255)
Reserved
Set up DAP coefficients bank
switching for banks 1, 2, and 3
Channel 1 delay = –23 DCLK periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = –16 DCLK periods
Channel 4 delay = 16 DCLK periods
Channel 5 delay = –24 DCLK periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = –8 DCLK periods
Channel 8 delay = 24 DCLK periods
Minimum absolute default = 0 DCLK periods
Manual selection – bank 1
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Serial-Control I²C Register Summary
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