TAS1020 Datasheet, PDF (69/93 Pages) Texas Instruments – USB Streaming Controller

A.5.2.2 DMA Time Slot Assignment Register (High-byte) (DMATSH1 – Address FFEFh)
(DMATSH0 – Address 0xFFE9)
Bit
Mnemonic
Type
Default
7
BPTS1
R/W
0
6
BPTS0
R/W
0
BIT MNEMONIC
NAME
7:6 BPTS(1:0)
Bytes per time slot
5:0 TSL(13:8)
Time slot assignment
5
TSL13
R/W
0
4
TSL12
R/W
0
3
TSL11
R/W
0
2
TSL10
R/W
0
1
TSL9
R/W
0
0
TSL8
R/W
0
DESCRIPTION
The bytes per time slot bits are used to define the number of bytes to be transferred for each
time slot supported by this DMA channel.
00b = 1 byte, 01b = 2 bytes, 10b = 3 bytes, 11b = 4 bytes
The DMA time slot assignment bits are set to 1 by the MCU to define the codec port
interface time slots supported by this DMA channel.
A.5.2.3 DMA Control Register (DMACTL1 – Address FFEEh) (DMACTL0 – Address FFE8h)
Bit
7
6
5
Mnemonic
DMAEN
HSKEN
—
Type
R/W
R/W
R
Default
0
0
0
4
3
2
1
0
—
EPDIR
EPNUM2
EPNUM1
EPNUM0
R
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT MNEMONIC
NAME
DESCRIPTION
7 DMAEN
DMA enable
The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before enabling
the DMA channel, all other DMA channel configuration bits must be set to the desired value.
6 HSKEN
Handshake enable
This bit is relevant for BULK data transfer in the OUT direction through DMA. MCU must set
this bit to a 1 to enable the handshake mode for the data transfer. If MCU sets this bit, MCU
has to enable DMA for each received BULK OUT packet. DMA, once enabled, transfers the
BULK OUT packet to the C-port, disables itself and generates an interrupt to the MCU. If
MCU clears this bit, DMA handles the BULK OUT data transfer to the C-port without MCU
intervention. For more details, refer to section 2.2.7.3.3.
5—
Reserved
Reserved for future use
4—
Reserved
Reserved for future use
3 EPDIR
USB end-point direction
The USB end-point direction bit controls the direction of data transfer by this DMA channel.
The MCU should set this bit to a 1 to configure this DMA channel to be used for a USB in
end-point. The MCU must clear this bit to a 0 to configure this DMA channel to be used for a
USB out end-point.
2:0 EPNUM(2:0)
USB end-point number
The USB end-point number bits are set by the MCU to define the USB end-point number
supported by this DMA channel. Keep in mind that end-point 0 is always used for the control
end-point, which is serviced by the MCU and not a DMA channel.
001b = End-Point 1, 010b = End-Point 2, …, 111b = End-Point 7
A.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L – Address FFE3h)
(DMABCNT0L– Address FFEBh)
Bit
Mnemonic
Type
Default
7
Size 7
R
0
6
Size 6
R
0
5
Size 5
R
0
4
Size 4
R
0
3
Size 3
R
0
2
Size 2
R
0
1
Size 1
R
0
0
Size 0
R
0
BIT MNEMONIC
NAME
7:0 Size(7:0)
Buffer content
DESCRIPTION
This register shows the buffer content (bytes) for an ISO OUT end-point. This register is updated
every SOF and is stable for the following USB frame which MCU can read it to implement USB
audio synchronization.
A–21