TMS320UC5405 Datasheet, PDF (68/77 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 6−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)^†
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
t_{su(BDRV-BCKXH)}
t_{h(BCKXH-BDRV)}
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
16
− 12H
ns
4
12H + 5
ns
t_{su(BFXL-BCKXL)}
Setup time, BFSX low before BCLKX low
10
ns
t_c(BCKX)
Cycle time, BCLKX
12H
32H
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
Table 6−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)^†
PARAMETER
MASTER^‡
MIN MAX
SLAVE
UNIT
MIN
MAX
t_{h(BCKXH-BFXL)}
t_{d(BFXL-BCKXL)}
t_{d(BCKXL-BDXV)}
t_{dis(BCKXH-BDXHZ)}
Hold time, BFSX low after BCLKX high^§
Delay time, BFSX low to BCLKX low^¶
Delay time, BCLKX low to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX high
T−4 T+5
ns
D−6 D+4
ns
−3
7 6H + 6 10H + 20 ns
D−2 D+3
ns
t_{dis(BFXH-BDXHZ)}
Disable time, BDX high impedance following last data bit from
BFSX high
2H + 7 6H + 21 ns
t_d(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H − 3 8H + 21 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{T = BCLKX period = (1 + CLKGDV) * 2H}
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
BFSX
BDX
BDR
LSB
t_{su(BFXL-BCKXL)}
MSB
t_c(BCKX)
t_{h(BCKXH-BFXL)}
t_{d(BFXL-BCKXL)}
Bit 0
Bit 0
t_{dis(BFXH-BDXHZ)}
t_{dis(BCKXH-BDXHZ)}
t_{su(BDRV-BCKXH)}
t_d(BFXL-BDXV)
Bit(n-1)
Bit(n-1)
t_{d(BCKXL-BDXV)}
(n-2)
(n-3)
t_{h(BCKXH-BDRV)}
(n-2)
(n-3)
(n-4)
(n-4)
Figure 6−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
68 SPRS199B
October 2002 − Revised October 2004