AFE5812_15 Datasheet, PDF (67/109 Pages) Texas Instruments – AFE5812 Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, and Digital I/Q Demodulator, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 180 mW/CH

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AFE5812
SLOS816A – MARCH 2015 – REVISED MARCH 2015
1. Serializer configuration:
– Serialization Factor 0x03[14:13]: It can be set using demodulator register SERZ_FACTOR. Default
serialization factor for the demodulator is 16×. However, the actual LVDS clock speed can be set by the
serialization factor in the ADC SPI interface as well; the ADC serialization factor is adjusted to 14× by
default. Therefore, it is necessary to sync these two settings when the demodulator is enabled, that is, set
the ADC register 0x03[14:13] = 01.
– Output Resolution 0x03[11:9]: In the default setting, it is 14 bits. The demodulator output resolution
depends on the decimation factor. 16-bit resolution can be used when higher decimation factor is
selected.
– For RF mode (passing 14 bits only), demodulator serialization factor can be changed to 14× by setting
demodulator register 0xC3[14:13] to 10.
2. Channel selection:
– Using register MODULATE_BYPASS 0x0A[14], channel output mode can be selected as IQ modulated or
single-channel I or Q output.
– Channel output is also selected using registers OUTPUT_CHANNEL_SEL 0x0A[11] and
FULL_LVDS_MODE 0x0A[9] and decimation factor.
– Each of the two demodulator subchips in a device has four channels named A, B, C, and D.
NOTE
After decimation, the LVDS FCLK rate keeps the same as the ADC sampling rate.
Considering the reduced data amount, zeros are appended after I and Q data and ensure
the LVDS data rate matches the LVDS clock rate. For detailed information about channel
multiplexing, see Table 14. In the table, A.I refers to CHA in-phase output, and A.Q refers
to CHA quadrature output. For example, M = 3, the valid data output rate is Fs / 3 for both
I and Q channels, that is 2 × Fs / 3 bandwidth is occupied. The left Fs / 3 bandwidth is
then filled by M-2 zeros. As a result, the demod LVDS output data are A.I, A.Q, 0, A.I A.Q
0 after SYNC_WORD, FCLK = Fs and DCLK = Fs × 8. When two ADC CHs' data are
transferred by one LVDS lane, M-4 zeros are filled after A.I, A.Q, B.I, and B.Q. See more
details in Table 14 and Figure 89.
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