TAS5508B Datasheet, PDF (65/106 Pages) Texas Instruments – 8-Channel Digital Audio PWM Processor

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TAS5508B
8-Channel Digital Audio PWM Processor
SLES162B – DECEMBER 2005 – REVISED APRIL 2006
4.8.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
64 f_S is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit
data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508B masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
LRCLK
32 Clks
Left Channel
32 Clks
Right Channel
SCLK
MSB
24-Bit Mode
20-Bit Mode
16-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
LSB MSB
10
10
10
23 22
19 18
15 14
19 18
15 14
15 14
Figure 4-12. Right-Justified 64-f_S Format
LSB
10
10
10
T0034-03
Electrical Specifications
65