ADS5296 Datasheet, PDF (65/104 Pages) Texas Instruments – 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter

ADS5296
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Bit D0
PAT_DESKEW_SYNC0
0 = Inactive
1 = Deskew pattern mode enabled; ensure that D1 is '0'
SBAS606A – MAY 2013 – REVISED MAY 2013
Table 38. Register 46h
D15
D14
D13
D12
D11
D10
D9
D8
ENABLE 46
0
FALL_SDR
0
EN_BIT_SER
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
EN_SDR
EN_MSB_
FIRST
BTC_MODE
0
0
All bits default to '0' after reset. Note that bit D15 must be set to '1' to enable bits D[13:0].
Bit D15
Bit D14
Bit D13
Bit D12
Bits D[11:8]
Bits D[7:5]
Bit D4
Bit D3
Bit D2
Bit D[1:0]
ENABLE 46
0 = Disable bits D13, D[11:8] and D[4:2] of register 46h
1 = Enable bits D13, D[11:8] and D[4:2] of register 46h
Must write '0'
FALL_SDR
0 = The LCLK rising or falling edge comes at the edge of the data window when operating in
SDR output mode
1 = The LCLK rising or falling edge comes in the middle of the data window when operating
in SDR output mode
Must write '0'
EN_BIT_SER
0001 = 10-bit serialization mode enabled
0010 = 12-bit serialization mode enabled
0100 = 14-bit serialization mode enabled
Do not use any other bit combinations.
Must write '0'
EN_SDR
0 = DDR bit clock
1 = SDR bit clock
EN_MSB_FIRST
0 = LSB first
1 = MSB first
BTC_MODE
0 = Binary offset (ADC data output format)
1 = Twos complement (ADC data output format)
Must write '0'
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