UCC28632_15 Datasheet, PDF (64/79 Pages) Texas Instruments – High-Power Flyback Controller with Primary-Side Regulation and Peak-Power Mode

UCC28630
UCC28631
UCC28632, UCC28633
SLUSBW3C – MARCH 2014 – REVISED MARCH 2015
www.ti.com
Thus, knowing L_P and C_P, the power stage impedance Z_LC(bias) (reflected to the bias winding) may be calculated
from Equation 66, and the effective wake resistance can be referred to the bias winding using Equation 67. The
wake pulse amplitude can be calculated from Equation 68. If C_P is not known, it can be measured by observing
the resonant ring period at the primary drain node, T_RES, and calculating C_P from Equation 69. Worst case values
should be used to estimate the worst case minimum wake pulse amplitude at the VSENSE pin. It should also be
noted that any filter cap on the VSENSE pin (including internal parasitic pin capacitance) adds an RC filter in
conjunction with the Thevenin resistance of the VSENSE divider, R_T, R_B; this delays and further attenuate the
wake pulse amplitude. Additionally, the internal wake comparator requires some over-drive to trip, and exhibits
propagation delay that depends on the amount of overdrive. So some margin should be allowed in the wake
pulse amplitude to ensure that the minimum wake pulse can adequately overdrive the internal wake comparator.
A margin of at least 20% over the threshold V_SENSE(wake) is recommended.
<_{.%(>E=O )}
=
¨^.2
%₂
×
l^0$p²
0₂
4_{9#-' (>E=O )}
=
4_9#-'
×
l^0$
2
p
0₅
(66)
(67)
8_{5'05' _9#-' (LG )}
=
l ^4$ p
4_# + 4_$
×
l8₁₇₆
×
(1
F
¿_{9#-' %})
×
0_$p
0₅
×
.
<_{.%(>E=O )}
/
<_{.%(>E=O )} + 4_{9#-' (>E=O )}
(68)
%₂
=
l^6NAO
2
p
2è
×
1
.₂
(69)
If the worst case wake pulse amplitude is too low, then the UCC24650 WAKE output can be augmented with an
external PNP circuit Q1, R1 and R2, as shown in Figure 40. This circuit reduces the effective wake resistance to
ground, so that a larger proportion of the output voltage appears across the transformer secondary pins when the
UCC24650 WAKE activates.
Using the UCC28630EVM-572, (TI Literature Number SLUUAX9) circuit parameters from Figure 44, the nominal
wake pulse amplitude at the VSENSE pin can be estimated. Of course, the rectifying diode D7 in Figure 44
would need to be relocated to return end of the secondary winding (pins 10, 11) to allow UCC24650 to be
deployed.
From observation of the DCM ringing period, the period T_RES was found to be 1.138 μs. From Equation 69, C_P is
estimated:
%₂
=
l^6NAO
2
p
2è
×
1
.₂
=
1.138ä ²
l
p
2è
×
1
260ä
=
126
L(
(70)
From Equation 66, the power circuit impedance is:
<_{.%(>E=O )}
=
¨^.2
%₂
×
l^0$
2
p
0₂
=
260ä
¨
126L
×
4²
lp
34
=
19.9
:
(71)
The WAKE pin resistance R_WAKE can be determined form the UCC24650 datasheet; for now a nominal value of
400 Ω is assumed. Referred to the bias winding (scaled by (N_B/N_S)²), this becomes 178 Ω. Similarly Δ_WAKE% can
be determined from the UCC24650 datasheet; for now, a value of 97% is assumed. From Equation 68, the wake
pulse amplitude can be calculated:
8_5'05'9#-'
:LG ;
=
l ^4$ p
4_# + 4_$
×
l8₁₇₆
×
¿_{9#-' %}
×
0_{$ p}
0₅
×
F
<_{.%:>E=O ;}
G
<_{.%:>E=O ;} + 4_{9#-' :>E=O ;}
32.05
4
19.9
= l_{22.6 + 32.05}p × l19.5 × 97% × ₆p × l_{19.9 + 178}p = 0.743 8
(72)
In this case, the VSENSE wake pulse amplitude would be insufficient to trip the internal wake comparator. If the
power stage had higher L_P, or lower C_P, a larger wake pulse would be produced.
64
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