TAS5508 Datasheet, PDF (63/101 Pages) Texas Instruments – 8 Channel Digital Audio PWM Processor

I²C Serial Control Interface (Slave Address 0x36)
4 I²C Serial Control Interface (Slave Address 0x36)
The TAS5508 has a bidirectional I²C interface that compatible with the I²C (Inter IC) bus protocol and supports
both 100 Kbps and 400 Kbps data transfer rates for single and multiple byte write and read operations. This
is a slave only device that does not support a multi-master bus environment or wait state insertion. The control
interface is used to program the registers of the device and to read device status.
The TAS5508 supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus
operation (400 kHz maximum). The TAS5508 performs all I²C operations without I²C wait cycles.
4.1 General I²C Operation
The I²C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred
in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on
the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and
stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 4 - 1. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5508 holds SDA low during
acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next
byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All
compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
SDA
7 Bit Slave Address
R/
W
A
8 Bit Register Address (N)
A
8 Bit Register Data For
Address (N)
A
8 Bit Register Data For
Address (N)
A
SCL
76543210
76543210
76543210
76543210
Start
Stop
Figure 4 - 1. Typical I²C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the
last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
is shown in Figure 4 - 1.
The 7-bit address for the TAS5508 is 0011011.
4.2 Single and Multiple Byte Transfers
The serial control interface supports both single-byte and multiple-byte read / write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data processing
registers, the serial control interface supports only multiple byte (4 byte) read / write operations.
During multiple byte read operations, the TAS5508 responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular
subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple byte write operations, the TAS5508 compares the number of bytes transmitted to the number
of bytes that are required for each specific sub address. If a write command is received for a biquad
subaddress, the TAS5508 expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
Similarly, if a write command is received for a mixer coefficient, the TAS5508 expects to receive one 32-bit
word.
SLES091B — February 2004 - Revised June 2004
TAS5508
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