TMS320AV7110 Datasheet, PDF (60/131 Pages) Texas Instruments – Integrated Digital Set-top Box Decoder Functional Specification

DSP
TMS320AV7110
Revision 3.1
12. Extension Bus Interface (EBI)
The extension bus interface is a 32-bit or 16-bit bi-directional data bus with a 25-bit address. It also
provides 3 external interrupts and a wait line. All the external memories or I/O devices are mapped to
the 32-bit address space of the ARM. There are six internally generated Chip Selects (CSx) for devices
such as EPROM memory, modem, front panel, front end control, parallel output port, and 1394 Link
device. Each CS has its own defined memory space and a programmable wait register which has a
default of maximum allowable values as defined in Table 31. The number of wait states depends on the
content of the register, with a minimum of one wait state. The EXTWAIT signal can also be used to
lengthen the access time if a slower device exists in that memory space. These are all programmable by
the application software using APIs.
The active low output signal EXTOE/EXTACTIVE is user selectable to be either asserted during EBI
read cycles only (EXTOE), the default selection, or asserted for both read and write cycles
(EXTACTIVE). This signal equals the logical AND of all the chip selects as well as DRAM access on
the EBI. The timing relationship of this signal with respect to other signals can be found in Section
17.1.
When the 32-bit EBI mode is selected and the ARM is operating in Thumb mode, instruction pre-fetch
is supported. Each instruction fetch by the ARM to the external memory on the EBI will transfer two
16-bit instructions. One is sent immediately to the ARM and the other is stored in a local register to
service the next instruction access.
During the Reset of the ‘AV7110, all EBI signals are held in a tri-state condition until the Reset signal
is released. Note that this includes the full 32-bit version of the EBI because the device does not
configure the bus for 16 or 32 bit operation until it comes out of reset. External pull-up resistors are
required on the control logic to prevent falsely enabling external devices during reset. Furthermore,
roughly 10 kΩ pull-up resistors are recommended for the address and data lines as well to prevent
problems associated with “floating” busses.
12.1 Address Range and Wait State of Chip Select
The Extension Bus supports the connection of 6 devices using the pre-defined chip selects. Additional
devices may be used by externally decoding the address bus. Table 31 shows the name of the device,
its chip select, address range, and programmable wait state range. Every device connected to the EBI is
required to have tri-stated data outputs within 1 clock cycle (CLK40) following the removal of chip-
select. DMA accesses to the EBI are interleaved with ARM based accesses. This one clock cycle (24
nanoseconds) constraint is to ensure a correct DRAM write when interleaved with DMA transfers. The
tri-state timing requirement after other transactions (including DRAM) is 2 clock cycles or 48 nssec.
with one exception. An ARM access to EPROM (CS1 region) during a DMA transfer to the EBI. This
transaction requires the 24 ns restriction between DMA access and CS1 access because of the priority
of code fetches to the ARM.
10/08/99 22:18
Page 60