TSL215 Datasheet, PDF (6/11 Pages) Texas Instruments – 128 × 1 INTEGRATED OPTO SENSOR

TSL215
128 × 1 INTEGRATED OPTO SENSOR
SOES005A – JUNE 1992 – REVISED AUGUST 1993
electrical characteristics , V_DD = 5 V, T_A = 25°C, f_clock = 180 kHz, λ_p = 565 nm, R_L = 330 Ω, C_L = 330 pF,
t_int = 5 ms, E_e = 20 µW/cm² (unless otherwise noted) (see Note 3)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
Low-level output voltage
High-level output voltage
Analog output voltage, saturation level
Analog output voltage (white, average over 64 pixels)
IO = 0
Ee = 60 µW/cm2
0.1 V
4.4
V
3 3.4
V
1.75 2.2
V
Analog output voltage (dark, each pixel)
Output voltage (white) change with change in VDD
Dispersion of analog output voltage
Ee = 0
VDD = 5 V ± 5%,
See Note 5
See Note 4
0.25 0.4 V
± 2%
±10%
Linearity of analog output voltage
Pixel recovery time
tint = 2 ms to 5 ms, See Note 6 0.85
See Note 7
1.15
25
40 ms
Supply current
IDD (average),
See Note 4
4
12 mA
High-level input current
VI = VDD
0.5 µA
Low-level input current
VI = 0
0.5 µA
Input capacitance
5
pF
† _{All typical values are at VDD = 5 V and TA = 25°C.}
NOTES: 3. The input irradiance (Ee) is supplied by an LED array with λ_p = 565 nm.
4. Device tested in parallel mode with only one section active
5. Dispersion of analog output voltage is the maximum difference between the voltage from any single pixel and the average output
voltage from all pixels of the device under test.
6. Linearity of analog output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage
at 2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and 5 ms.
7. Pixel recovery time is the time required for a pixel to go from the analog-output-voltage (white, average over 64 pixels) level to
analog-output-voltage (dark, each pixel) level or vice versa after a step change in light input.
operating characteristics, R_L = 330 Ω, C_L = 330 pF, V_DD = 5 V, T_A = 25°C, t_int = 5 ms,
E_e = 20 µW/cm², f_clock = 500 kHz (unless otherwise noted)
PARAMETER
tr(SO) Rise time, SO
tf(SO) Fall time, SO
tpd(SO) Propagation delay time, SO
ts
Settling time
tv
Valid time
NOTE 8: Clock duty cycle is assumed to be 50%.
TEST CONDITIONS
MIN TYP MAX
25
25
See Figure 3 and Note 8
70
1
1/2 fclock
UNIT
ns
ns
ns
µs
µs
6
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