TPS70751-EP_15 Datasheet, PDF (6/42 Pages) Texas Instruments – DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS

TPS70751-EP
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR
WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS
SLVS718 – DECEMBER 2006
www.ti.com
Power Good (PG1)
The PG1 terminal is an open-drain, active-high output terminal that indicates the status of the V_OUT1 regulator.
When the V_OUT1 reaches 95% of its regulated voltage, PG1 goes into a high-impedance state. PG1 goes into a
low-impedance state when V_OUT1 is pulled below 95% (i.e., overload condition), of its regulated voltage. The
open-drain output of the PG1 terminal requires a pullup resistor.
Manual Reset (MR1 and MR2)
MR1 and MR2 are active-low input terminals used to trigger a reset condition. When either MR1 or MR2 is
pulled to logic low, a POR (RESET) occurs. These terminals have a 6-µA pullup current to V_IN1.
Sense (V_SENSE1, V_SENSE2)
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers through
a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the
sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the V_SENSE
terminals and V_OUT terminals to filter noise is not recommended because it can cause the regulators to oscillate.
Feedback (FB1 and FB2)
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and V_OUT
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
RESET Indicator
The TPS70751 features a RESET (SVS, POR, or power-on reset). RESET can be used to drive power-on reset
circuitry or a low-battery indicator. RESET is an active-low, open-drain output that indicates the status of the
V_OUT2 regulator and both manual reset (MR1 and MR2) pins. When V_OUT2 exceeds 95% of its regulated voltage,
and MR1 and MR2 are in the high-impedance state, RESET goes to a high-impedance state after a 120-ms
delay. RESET goes to a low-impedance state when V_OUT2 is pulled below 95% (i.e., overload condition) of its
regulated voltage. To monitor V_OUT1, the PG1 output can be connected to MR1 or MR2. The open-drain output
of RESET requires a pullup resistor. If RESET is not used, it can be left floating.
Input Voltage (V_IN1 and V_IN2)
V_IN1 and V_IN2 are inputs to the regulators. Internal bias voltages are powered by V_IN1.
Output Voltage (V_OUT1 and V_OUT2)
V_OUT1 and V_OUT2 are output terminals.
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