TPS3307-18-Q1 Datasheet, PDF (6/12 Pages) Texas Instruments – TRIPLE PROCESSOR SUPERVISORS

TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
timing requirements at V_DD = 2 V to 6 V, R_L = 1 MΩ, C_L = 50 pF, T_A = 25°C
PARAMETER
TEST CONDITIONS
MIN
SENSEn
tw
Pulse width
MR
VSENSEnL = VIT_– –0.2 V,
VIH = 0.7 × VDD,
VSENSEnH = VIT+ +0.2 V
VIL = 0.3 × VDD
6
100
TYP MAX UNIT
10
µs
150
ns
switching characteristics at V_DD = 2 V to 6 V, R_L = 1 MΩ, C_L = 50 pF, T_A = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
td
tPHL
tPLH
Delay time
Propagation (delay) time,
high-to-low level output
Propagation (delay) time,
low-to-high level output
MR to RESET
MR to RESET
MR to RESET
MR to RESET
VI(SENSEn) ≥ VIT+ + 0.2 V,
MR ≥ 0.7 × VDD, See timing diagram
140 200 280 ms
VI(SENSEn) ≥ VIT+ +0.2 V,
VIH = 0.7 × VDD, VIL = 0.3 × VDD
200 600 ns
tPHL
tPLH
Propagation (delay) time,
high-to-low level output
Propagation (delay) time,
low-to-high level output
SENSEn to RESET
SENSEn to RESET
VIH = VIT+ +0.2 V, VIL = VIT_– –0.2 V,
MR ≥ 0.7 × VDD
1
5 µs
6
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