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| TPA2026D2_15 Datasheet, PDF (6/39 Pages) Texas Instruments – 3.2-W/Ch Stereo Class-D Audio Amplifier with Fast Gain Ramp SmartGain™ AGC/DRC | |||
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TPA2026D2
SLOS649A â MARCH 2010 â REVISED JANUARY 2011
I2C TIMING CHARACTERISTICS
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
fSCL
Frequency, SCL
No wait states
tW(H)
Pulse duration, SCL high
0.6
tW(L)
Pulse duration, SCL low
1.3
tSU(1)
Setup time, SDA to SCL
100
th1
Hold time, SCL to SDA
10
t(buf)
Bus free time between stop and start
1.3
condition
tSU2
Setup time, SCL to start condition
0.6
th2
Hold time, start condition to SCL
0.6
tSU3
Setup time, SCL to stop condition
0.6
SCL
tw(H)
tw(L)
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MAX
400
UNIT
kHz
ms
ms
ns
ns
ms
ms
ms
ms
SDA
SCL
SDA
t su1
th1
Figure 1. SCL and SDA Timing
th2
tsu2
t(buf)
tsu3
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions Timing
6
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Copyright © 2010â2011, Texas Instruments Incorporated
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