TMS370CX4X Datasheet, PDF (6/66 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C – NOVEMBER 1992 – REVISED FEBRUARY 1997
central processing unit (CPU)
The CPU used on the TMS370Cx4x device is the high-performance 8-bit TMS370 CPU module. The ’x4x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x4x instruction map is shown in Table 17 in the TMS370Cx4x instruction set overview
section.
The ’370Cx4x CPU architecture provides the following components:
D CPU registers:
– A stack pointer (SP) that points to the last entry in the memory stack
– A status register (ST) that monitors the operation of the instructions and contains the
global-interrupt-enable bits
– A program counter (PC) that points to the memory location of the next instruction to be executed
Figure 1 illustrates the CPU registers and memory blocks.
15
Program Counter
0
7
Stack Pointer (SP)
0
Status Register (ST)
C N Z V IE2 IE1
7 6 543 210
RAM (Includes up to 256-Byte Registers File)
0000h
0001h
0002h
0003h
R0(A)
R1(B)
R2
R3
007Fh
R127
Legend:
C=Carry
N=Negative
Z=Zero
V=Overflow
IE2=Level 2 interrupts Enable
IE1=Level 1 interrupts Enable
256-Byte RAM (0000h–00FFh)
Reserved†
Peripheral File
Reserved†
256-Byte Data EEPROM
Not Available‡
8K-Byte ROM/EPROM (6000h – 6FFFh)
4K-Byte ROM (7000h – 7FFFh)
00FFh
R255
† _{Reserved means the address space is reserved for future expansion.}
‡ _{Not available means the address space is not accessible.}
Interrupts and Reset Vectors;
Trap Vectors
Figure 1. Programmer’s Model
0000h
00FFh
0100h
0FFFh
1000h
10FFh
1100h
1EFFh
1F00h
1FFFh
2000h
5FFFh
6000h
6FFFh
7000h
7FBFh
7FC0h
7FFFh
6
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443