TLC2932AIPWRG4 Datasheet, PDF (6/23 Pages) Texas Instruments – HIGH PERFORMANCE PAHSE LOCKED LOOP

TLC2932A
HIGH PERFORMANCE PHASE LOCKED LOOP
SLES150 − OCTOBER 2005
electrical characteristics, V_DD = 3 V, T_A = 25°C (unless otherwise noted) (continued)
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
High level output voltage
IOH = –2 mA
2.4
V
VOL
Low level output voltage
IOL = 2 mA
0.3 V
IOZ
High impedance state output current
PFD inhibit = high, VO = VDD or GND
±1 µA
VIH
High level input voltage at Fin−A, Fin−B
2.1
V
VIL
Low level input voltage at Fin−A, Fin−B
0.5 V
VTH
Input threshold voltage at PFD inhibit
0.9
1.5
2.1
CIN
Input capacitance at Fin−A, Fin−B
5.6
pF
ZIN
Input impedance at Fin−A, Fin−B
10
MΩ
IDD(Z)
High impedance state PFD supply current See Note 6
1 µA
IDD(PFD) PFD supply current
See Note 7
3 mA
NOTES: 6. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD
OUT open, and VCO OUT is inhibited.
operation characteristics, V_DD = 3 V, T_A = 25°C (unless otherwise noted)
VCO section
Parameter
TEST CONDITIONS
MIN
TYP
MAX UNIT
fOSC
fSTB
tr
tf
α (fOSC)
Operation oscillation frequency
Time to stable oscillation (see Note 8)
Rise time
Fall time
Duty cycle at VCO OUT
Temperature coefficient of oscillation
frequency
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
17
25
CL = 15 pF
CL = 15 pF
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
VCO IN = 1/2 VDD, TA = –20°C to
75°C
45%
9
7.6
50%
–0.264
33
10
14
12
55%
MHz
µs
ns
ns
%/°C
kSVS
(fosc)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 VDD, VDD = 4.75 V to
5.25 V
0.004
%/mV
NOTES:
Jitter absolute (see Note 9)
PLL jitter, N = 128
325
ps
8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
fmax
tPLZ
tPHZ
tPZL
tPZH
tr
tf
PARAMETER
Maximum operation frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
Fall time
TEST CONDITIONS
CL = 15 pF
CL = 15 pF
MIN
TYP
MAX UNIT
17
MH
22
50
ns
21
50
ns
6.5
30
ns
7
30
ns
3.4
10
ns
1.9
10
ns
6
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