SN65LVDS100 Datasheet, PDF (6/20 Pages) Texas Instruments – DIFFERENTIAL TRANSLATOR/REPEATER

SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
V_OY
+
V_OD
-
V_OZ
50 Ω
50 Ω
+
-
V_CC - 2V
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Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101)
A
V_ID
V_IA
B
V_IB
Y
1 pF
Z
V_IA
V_OD
100 Ω
V_IB
V_ID
V_OD ^{50 Ω}
OR
50 Ω
+
-
V_CC - 2V
t_PHL
V_OD
80%
t_f
20%
t_r
1.4 V
1V
0.4 V
0V
-0.4 V
t_PLH
100%
0V
0%
NOTE: All input pulses are supplied by a generator having the following characteristics: t_r or t_f ≤ 0.25 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C_L includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 5. Timing Test Circuit and Waveforms
CLOCK INPUT
0V
1/fo
ACTUAL OUTPUT
0V
Period Jitter
t_c(n)
t_jit(per) = |t_c(n) - 1/fo|
IDEAL OUTPUT
0V
1/fo
ACTUAL OUTPUT
0V
Cycle to Cycle Jitter
t_c(n)
t_c(n+1)
t_jit(cc) = |t_c(n) - t_c(n+1)|
PRBS INPUT _{0 V}
PRBS OUTPUT _{0 V}
t_jit(pp)
Figure 6. Driver Jitter Measurement Waveforms
6