SN65LVCP40_07 Datasheet, PDF (6/23 Pages) Texas Instruments – DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER

SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
www.ti.com
Table 1. Signal Descriptions
SIGNAL PIN(S)
TYPE
SIGNAL TYPE
DESCRIPTION
LINE SIDE HIGH-SPEED I/O
LI_0P
6
LI_0N
7
I (w/ 50-Ω termination PECL/CML
to VBB)
compatible
Differential input, port_0 line side
LI_1P
30
LI_1N
31
I (w/ 50-Ω termination PECL/CML
to VBB)
compatible
Differential input, port_1 line side
LO_0P
33
LO_0N
34
O
VML ⁽¹⁾
Differential output, port_0 line side
LO_1P
9
LO_1N
10
O
VML ⁽¹⁾
Differential output, port_1 line side
SWITCH SIDE HIGH-SPEED I/O
SIA_0P
40
SIA_0N
39
I (w/ 50-Ω termination CML/PECL
to VBB)
compatible
Differential input, mux_0 switch_A_side
SIB_0P
43
SIB_0N
42
I (w/ 50-Ω termination CML/PECL
to VBB)
compatible
Differential input, mux_0 switch_B_side
SIA_1P
16
SIA_1N
15
I (w/ 50-Ω termination CML/PECL
to VBB)
compatible
Differential input, mux_1 switch_A_side
SIB_1P
19
SIB_1N
18
I (w/ 50-Ω termination CML/PECL
to VBB)
compatible
Differential input, mux_1 switch_B_side
SOA_0P 46
SOA_0N 45
O
VML ⁽¹⁾
Differential output, mux_0 switch_A_side
SOB_0P 4
SOB_0N 3
O
VML ⁽¹⁾
Differential output, mux_0 switch_B_side
SOA_1P 22
SOA_1N 21
O
VML ⁽¹⁾
Differential output, mux_1 switch_A_side
SOB_1P 28
SOB_1N 27
O
VML ⁽¹⁾
Differential output, mux_1 switch_B_side
CONTROL SIGNALS
PREL_0 12
PREL_1 1
I (w/ 35-kΩ pullup) LVTTL
Output preemphasis control, line side port_0 and port_1. Has internal
pull-up. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and
PRES for function definition.
PRES_0 36
PRES_1 25
I (w/ 35-kΩ pullup) LVTTL
Output preemphasis control, switch side port_0 and port_1. See
Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for
function definition.
LB0A
LB0B
47
48
I (w/ 35-kΩ pullup) LVTTL
Loopback control for mux_0 switch side. See Loopback Controls LB0A,
LB0B, LB1A and LB1B for function definition.n
LB1A
LB1B
23
24
I (w/ 35-kΩ pullup) LVTTL
Loopback control for mux_1 switch side. See Loopback Controls LB0A,
LB0B, LB1A and LB1B for function definition.n
MUX_S0 37
MUX_S1 13
I (w/ 35-kΩ pullup) LVTTL
Port A and B multiplex control of mux_0 and mux_1. See Multiplex
Controls MUX_S0 and MUX_S1 for function definition.
REXT
26
N/A
No connect. This pin is unused and can be left open or tied to GND with
any resistor.
POWER SUPPLY
VCC
2, 8, 14,
20, 29,
35, 38,
44
PWR
Power supply 3.3 V ±5%
GND
5, 11, 17,
32, 41
PWR
Power supply return
GND
Center Pad
PWR
The ground center pad is the metal contact at the bottom of the 48-pin
package. It must be connected to the GND plane. At least 4 vias are
recommended to minimize inductance and provide a solid ground. See
the package drawing for the via placement.
(1) VML stands for Voltage Mode logic; VML provides a differential output impedance of 100-Ω. VML offers the benefits of CML and
consumes less power.
6
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