SN54AHC594 Datasheet, PDF (6/17 Pages) Texas Instruments – 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS

SN54AHC594, SN74AHC594
8ĆBIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
SN54AHC594 SN74AHC594
MIN TYP MAX MIN MAX MIN MAX
2V
1.9
2
1.9
1.9
VOH
IOH = −50 mA
IOH = −4 mA
3V
2.9
3
2.9
2.9
4.5 V
4.4 4.5
4.4
4.4
3V
2.58
2.48
2.48
QH_′, IOH = −4 mA
QA−QH, IOH = −8 mA
3.94
4.5 V
3.94
3.8
3.8
3.8
3.8
2V
0.1
0.1
0.1
VOL
IOL = 50 mA
IOL = 4 mA
3V
4.5 V
3V
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.5
0.44
QH_′, IOL = 4 mA
QA−QH, IOL = 8 mA
4.5 V
0.36
0.5
0.44
0.36
0.5
0.44
II
VI = 5.5 V or GND
0 V to 5.5 V
±0.1
±1*
±1
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
40
40
Ci
VI = VCC or GND
5V
2
10
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
UNIT
V
V
mA
mA
pF
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHC594 SN74AHC594
UNIT
MIN MAX MIN MAX MIN MAX
tw Pulse duration
RCLK or SRCLK high or low
RCLR or SRCLR low
5.5
5.5
5.5
ns
5
5
5
SER before SRCLK↑
SRCLK↑ before RCLK↑^†
3.5
3.5
3.5
8
8.5
8.5
tsu Setup time
SRCLR low before RCLK↑
8
9
9
ns
SRCLR high (inactive) before SRCLK↑
4.2
4.8
4.8
RCLR high (inactive) before RCLK↑
4.6
5.3
5.3
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† _{This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift}
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
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