MSP50C614 Datasheet, PDF (6/9 Pages) Texas Instruments – MIXED-SIGNAL PROCESSOR

MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
dc electrical characteristics, T_A = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP^§ MAX UNIT
Positive going threshold
2.4
RESET
Threshold changes
VDD = 3 V
Negative going threshold
Hysteresis
Positive going threshold
1.8
V
0.6
3.3
VDD = 5.2 V
Negative going threshold
Hysteresis
2.9
V
0.4
VIH
VIL
IOH^¶
High-level input
voltage
Low-level input
voltage
High-level output
current per pin of I/O
port
VDD = 3 V
VDD = 4.5 V
VDD = 5.2 V
VDD = 3 V
VDD = 4.5 V
VDD = 5.2 V
VOH = 4 V
2
3
3
4.5 V
3.5
5.2
0
1
0
1.5 V
0
1.7
–2 mA
IOL^¶
Low-level output
current per pin of I/O
port
VDD = 4.5 V
VOL = 0.5 V
5 mA
IOH _(DAC)
High-level output
DAC current
VOH = 4 V
–10 mA
IOL _(DAC)
Low-level output
DAC current
VOL = 0.5 V
20 mA
Ilkg
Input leakage
current
Excludes OSCIN
1 µA
I(STANDBY)
IDD^†
I(SLEEP-deep)
I(SLEEP-mid)
I(SLEEP-light)
VIO
R(PULLUP)
Standby current
Operating current
Supply current
Input offset voltage
F port pullup
resistance
RESET is low
VDD = 4.5 V,
VDD = 4.5 V,
VDD = 4.5 V,
VDD = 4.5 V,
VDD = 4.5 V,
VDD = 5 V
FCLOCK = 12.32 MHz
DAC off,
ARM set,
DAC off,
ARM set,
DAC off,
ARM clear,
Vref = 1 to 4.25 V
OSC disabled
OSC enabled
OSC enabled
0.05
15
0.05
40
60
25
70 150
10 µA
mA
10
60 µA
100
50 mV
kΩ
∆f(RTO-trim) Trim deviation
RRTO = 470 kΩ, VDD = 4.5 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)^‡
± 1% ± 3%
∆f(RTO-volt) Voltage deviation
RRTO = 470 kΩ, VDD = 3.5 to 5.2 V,
fRTO = 8.192 MHz (PLL setting = 7 Ch)^‡
TA = 25°C,
± 1.5%
Temperature
∆f(RTO-temp) _deviation
RRTO = 470 kΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)^‡
± 0.03
%/°C
∆f(RTO-res)
Resistance deviation
VDD = 4.5 V,
TA = 25°C, R(OSC) = 470 kΩ at ± 1%,
fRTO = 8.192 MHz (PLL setting = 7 Ch)^‡
± 1%
† _{Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output}
and other outputs are open circuited.
‡ _{The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.}
§ _{Typical voltage and current measurement taken at 25°C}
¶ _{Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.}
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