MSP430G2X31_11 Datasheet, PDF(6/55 Page) Texas Instruments

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MSP430G2X31_11 Datasheet, PDF (6/55 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430G2x31

MSP430G2x21

SLAS694F â FEBRUARY 2010 â REVISED APRIL 2011

www.ti.com

Table 2. Terminal Functions

TERMINAL

NAME

NO.

I/O

N, PW RSA

DESCRIPTION

P1.0/

TA0CLK/

ACLK/

General-purpose digital I/O pin

I/O

Timer0_A, clock signal TACLK input

ACLK signal output

ADC10 analog input A0(1)

P1.1/

TA0.0/

General-purpose digital I/O pin

I/O Timer0_A, capture: CCI0A input, compare: Out0 output

ADC10 analog input A1(1)

P1.2/

TA0.1/

General-purpose digital I/O pin

I/O Timer0_A, capture: CCI1A input, compare: Out1 output

ADC10 analog input A2(1)

P1.3/

General-purpose digital I/O pin

ADC10CLK/

A3/

I/O

ADC10, conversion clock output(1)

ADC10 analog input A3(1)

VREF-/VEREF

ADC10 negative reference voltage(1)

P1.4/

SMCLK/

A4/

VREF+/VEREF+/

TCK

General-purpose digital I/O pin

SMCLK signal output

I/O ADC10 analog input A4(1)

ADC10 positive reference voltage(1)

JTAG test clock, input terminal for device programming and test

P1.5/

TA0.0/

A5/

SCLK/

TMS

General-purpose digital I/O pin

Timer0_A, compare: Out0 output

I/O ADC10 analog input A5(1)

USI: clock input in I2C mode; clock input/output in SPI mode

JTAG test mode select, input terminal for device programming and test

P1.6/

TA0.1/

A6/

SDO/

SCL/

TDI/TCLK

General-purpose digital I/O pin

Timer0_A, capture: CCI1A input, compare: Out1 output

I/O

ADC10 analog input A6(1)

USI: Data output in SPI mode

USI: I2C clock in I2C mode

JTAG test data input or test clock input during programming and test

P1.7/

A7/

SDI/

SDA/

TDO/TDI (2)

General-purpose digital I/O pin

ADC10 analog input A7(1)

I/O USI: Data input in SPI mode

USI: I2C data in I2C mode

JTAG test data output terminal or test data input during programming and test

XIN/

P2.6/

TA0.1

XOUT/

P2.7

Input terminal of crystal oscillator

I/O General-purpose digital I/O pin

Timer0_A, compare: Out1 output

I/O

Output terminal of crystal oscillator(3)

General-purpose digital I/O pin

RST/

NMI/

SBWTDIO

Reset

I Nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

TEST/

SBWTCK

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

Spy-Bi-Wire test clock input during programming and test

DVCC

1 15, 16 NA Supply voltage

DVSS

14 13, 14 NA Ground reference

QFN Pad

Pad NA QFN package pad connection to VSS recommended.

(1) MSP430G2x31 only

(2) TDO or TDI is selected via JTAG instruction.

(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

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