LMC555 Datasheet, PDF (6/21 Pages) National Semiconductor (TI) – CMOS Timer

LMC555
SNAS558J – FEBRUARY 2000 – REVISED MARCH 2013
APPLICATION INFORMATION
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MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot (Figure 5). The external capacitor is initially held
discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 V_S to the Trigger
terminal, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.
Figure 5. Monostable (One-Shot)
The voltage across the capacitor then increases exponentially for a period of t_H = 1.1 R_AC, which is also the time
that the output stays high, at the end of which time the voltage equals 2/3 V_S. The comparator then resets the
flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 6 shows the
waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are
both directly proportional to supply voltage, the timing internal is independent of supply.
V_CC = 5V
TIME = 0.1 ms/Div.
R_A = 9.1 kΩ
C = 0.01 µF
Top Trace: Input 5 V/Div.
Middle Trace: Output 5 V/Div.
Bottom Trace: Capacitor Voltage 2 V/Div.
Figure 6. Monostable Waveforms
Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the
desired t_H. The minimum pulse width for the Trigger is 20ns, and it is 400ns for the Reset. During the timing cycle
when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger
input is returned high at least 10µs before the end of the timing interval. However the circuit can be reset during
this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state
until a trigger pulse is again applied.
When the reset function is not use, it is recommended that it be connected to V₊ to avoid any possibility of false
triggering. Figure 7 is a nomograph for easy determination of RC values for various time delays.
NOTE
In monstable operation, the trigger should be driven high before the end of timing cycle.
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