DS90LV048A Datasheet, PDF (6/20 Pages) National Semiconductor (TI) – 3V LVDS Quad CMOS Differential Line Receiver

DS90LV048A
SNLS045B – JULY 1999 – REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION (continued)
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C_L includes load and test jig capacitance.
S₁ = V_CC for t_PZL and t_PLZ measurements.
S₁ = GND for t_PZH and t_PHZ measurements.
Figure 3. Receiver TRI-STATE Delay Test Circuit
Figure 4. Receiver TRI-STATE Delay Waveforms
TYPICAL APPLICATION
Balanced System
Figure 5. Point-to-Point Application
6
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