DS90CR288AMTDX Datasheet, PDF (6/24 Pages) Texas Instruments – 20 to 85 MHz Shift Clock Support, 50% Duty Cycle on Receiver Output Clock

DS90CR287, DS90CR288A
SNLS056G – OCTOBER 1999 – REVISED MARCH 2013
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
CLHT
CMOS/TTL Low-to-High Transition Time Figure 8
CHLT
CMOS/TTL High-to-Low Transition Time Figure 8
RSPos0
Receiver Input Strobe Position for Bit 0 Figure 20
f = 85 MHz
RSPos1
Receiver Input Strobe Position for Bit 1
RSPos2
Receiver Input Strobe Position for Bit 2
RSPos3
Receiver Input Strobe Position for Bit 3
RSPos4
Receiver Input Strobe Position for Bit 4
RSPos5
Receiver Input Strobe Position for Bit 5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin⁽²⁾ Figure 21
f = 85 MHz
RCOP
RxCLK OUT Period Figure 11
RCOH
RxCLK OUT High Time Figure 11
f = 85 MHz
RCOL
RxCLK OUT Low Time Figure 11
RSRC
RxOUT Setup to RxCLK OUT Figure 11
RHRC
RCCD
RPLLS
RxOUT Hold to RxCLK OUT Figure 11
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V⁽³⁾ Figure 13
Receiver Phase Lock Loop Set Figure 15
RPDD
Receiver Powerdown Delay Figure 18
Min
0.49
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4
3.5
3.5
3.5
5.5
Typ ⁽¹⁾
2
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
T
5
5
7
Max
3.5
3.5
1.19
2.87
4.55
6.23
7.91
9.59
11.27
50
6.5
6
9.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
μs
(1) Typical values are given for V_CC = 3.3V and T_A = +25°C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows
LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than 150 ps).
(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
6
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