CDC536 Datasheet, PDF (6/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
fclock
Clock frequency
When VCO is operating at four times the CLKIN frequency
When VCO is operating at double the CLKIN frequency
25
50
MHz
50 100
Input clock duty cycle
40% 60%
After SEL
50
Stabilization time†
After OE↓
After power up
50
µs
50
After CLKIN
50
† _{Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,}
a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Note 4 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
fmax
100
MHz
Duty cycle
Y
45% 55%
tphase _error‡
CLKIN↑
Y
–500 +500 ps
Jitter(pk-pk)
tsk(o)‡
CLKIN↑
Y
200 ps
0.5 ns
tsk(pr)
1 ns
tr
1.4 ns
tf
1.4 ns
‡ _{The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o), and tsk(pk) specifications}
are only valid for equal loading of all outputs.
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
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