CDC208_15_15 Datasheet, PDF (6/16 Pages) Texas Instruments – DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC208
ą
DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER
WITH 3ĆSTATE OUTPUTS
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
2 × VCC
S1
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
GND
(see Note A)
Input
(see Note B)
tPLH
Output
LOAD CIRCUIT FOR OUTPUTS
1.5 V
3V
1.5 V
0V
tPHL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
3V
Control
(low-level
1.5 V
1.5 V
enabling)
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPZH
Output
Waveform 2
S1 at 2 × VCC
(see Note C)
50% VCC
tPHZ
50% VCC
≈ VCC
20% VCC
VOL
80% VCC ^VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 1. Load Circuit and Voltage Waveforms
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