CD74HC164 Datasheet, PDF (6/7 Pages) Texas Instruments – High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register

CD74HC164, CD74HCT164
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Power Dissipation
Capacitance
(Notes 4, 5)
SYMBOL
C_PD
TEST
CONDITIONS V_CC (V)
-
5
25^oC
TYP MAX
47
-
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
-
pF
HCT TYPES
Propagation Delay,
CP to Q_n
t_PLH, t_PHL C_L = 50pF
4.5
-
36
45
C_L = 15pF
5
15
-
-
MR to Q_n
t_PLH, t_PHL C_L = 50pF
4.5
-
38
46
C_L = 15pF
5
16
-
-
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
Input Capacitance
C_IN
-
-
-
-
-
Maximum Clock Frequency
f_MAX
C_L = 15pF
-
54
-
-
Power Dissipation
Capacitance
(Notes 4, 5)
C_PD
-
5
49
10
10
54
ns
-
ns
57
ns
-
ns
22
ns
-
pF
-
MHz
10
pF
NOTES:
5. C_PD is used to determine the dynamic power consumption, per device.
6. P_D = V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
Test Circuits and Waveforms
t_rC_L
CLOCK
INPUT
90%
10%
t_H(H)
t_fC_L
50%
t_H(L)
DATA
INPUT
t_SU(H)
t_SU(L)
OUTPUT
t_REM
V_CC
SET, RESET
OR PRESET
t_TLH
90%
t_PLH
50%
t_THL
90%
50%
10%
t_PHL
IC
C_L
50pF
V_CC
GND
V_CC
50%
GND
GND
t_rC_L
CLOCK
INPUT
2.7V
0.3V
t_fC_L
1.3V
t_H(H)
t_H(L)
DATA
INPUT
t_SU(H)
1.3V
1.3V
1.3V
t_SU(L)
OUTPUT
t_REM
3V
SET, RESET
OR PRESET
t_TLH
90%
1.3V
t_PLH
1.3V
t_THL
90%
1.3V
10%
t_PHL
IC
C_L
50pF
3V
GND
3V
GND
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6