CD74AC174 Datasheet, PDF (6/7 Pages) Texas Instruments – Hex D Flip-Flop with Reset

CD74AC174, CD54/74ACT174
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case) (Continued)
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
SYMBOL
V_CC (V)
MIN
Propagation Delay, MR to Qn
t_PLH, t_PHL
1.5
-
3.3
5.2
TYP
MAX
MIN
TYP
MAX UNITS
-
165
-
-
181
ns
-
18.5
5.1
-
20.3
ns
5
3.7
-
13.2
3.6
-
14.5
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
37
-
-
37
-
pF
ACT TYPES
Propagation Delay, CP to Qn
t_PLH, t_PHL
5
3.6
(Note 10)
-
12.6
3.5
-
14
ns
Propagation Delay, MR to Qn
t_PLH, t_PHL
5
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
4
-
14.1
3.9
-
15.5
ns
-
-
10
-
-
10
pF
-
37
-
-
37
-
pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C_PD is used to determine the dynamic power consumption per flip-flop.
P_D = C_PD V_CC2 f_i + Σ (C_L + V_CC2 f_o) + V_CC ∆I_CC where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC =
supply voltage.
INPUT LEVEL
CP
GND
V_S
V_S
t_W
t_PHL
V_S
V_S
t_PLH
V_S
FIGURE 1. PROPAGATION DELAYS
INPUT LEVEL
MR
GND
INPUT
CP
(Q)
Q
V_S
V_S
t_W
t_PHL
V_S
t_REM
V_S
FIGURE 2. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
INPUT LEVEL
D
GND
INPUT LEVEL
CP
GND
V_S
t_SU(L)
V_S
V_S
t_H(L)
t_SU(H)
V_S
V_S
t_H(H)
V_S
FIGURE 3.
OUTPUT
DUT
R_L (NOTE)
500Ω
OUTPUT
LOAD
C_L
50pF
NOTE: For AC Series Only: When V_CC = 1.5V, R_L = 1kΩ.
AC
ACT
Input Level
Input Switching Voltage, V_S
Output Switching Voltage, V_S
V_CC
0.5 V_CC
0.5 V_CC
3V
1.5V
0.5 V_CC
FIGURE 4. PROPAGATION DELAY TIMES
6